Search the dblp DataBase

Publications of Author

1. Md. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar
   A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:90-95 [Conf]
   
2. Md. Rafiqul Islam, Morshed U. Chowdhury
   Eliminating of the Drawback of Existing Testing Technique of Easily Testable PLAs Using an Improved Testing Algorithm with Product Line Rearrangement. [Citation Graph (0, 0)][DBLP]
   CAINE, 2002, pp:239-242 [Conf]
   
3. Sajid Hussain, Md. Rafiqul Islam, Elhadi Shakshuki, M. S. Zaman
   Agent-Based Petroleum Offshore Monitoring Using Sensor Networks. [Citation Graph (0, 0)][DBLP]
   DEXA Workshops, 2006, pp:103-107 [Conf]
   
4. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury
   Reversible Logic Synthesis for Minimization of Full-Adder Circuit. [Citation Graph (0, 0)][DBLP]
   DSD, 2003, pp:50-54 [Conf]
   
5. Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam
   Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
   DSD, 2004, pp:603-606 [Conf]
   
6. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury
   A heuristic approach to synthesize Boolean functions using TANT network. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:373-376 [Conf]
   
7. Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam, Md. Mazder Rahman
   On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2004, pp:321-326 [Conf]
   
8. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Amin Ahsan Ali, Mohammad Musa Salehin Akon
   A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2003, pp:111-116 [Conf]
   
9. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury
   Synthesis of Full-Adder Circuit Using Reversible Logic. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:757-760 [Conf]
   
10. Md. Rafiqul Islam, Morshed U. Chowdhury, Wanlei Zhou
    An Innovative Spam Filtering Model Based on Support Vector Machine. [Citation Graph (0, 0)][DBLP]
    CIMCA/IAWTIC, 2005, pp:348-353 [Conf]
    
11. Md. Rafiqul Islam, Wanlei Zhou, Morshed U. Chowdhury
    Dynamic Feature Selection for Spam Filtering Using Support Vector Machine. [Citation Graph (0, 0)][DBLP]
    ACIS-ICIS, 2007, pp:757-762 [Conf]
    
12. Md. Rafiqul Islam, Wanlei Zhou
    Architecture of Adaptive Spam Filtering Based on Machine Learning Algorithms. [Citation Graph (0, 0)][DBLP]
    ICA3PP, 2007, pp:458-469 [Conf]
    
13. 
    Email Categorization Using (2+1)-Tier Classification Algorithms. [Citation Graph (, )][DBLP]
    
    
14. 
    MVGL Analyser for Multi-classifier Based Spam Filtering System. [Citation Graph (, )][DBLP]
    
    
15. 
    Minimizing the Limitations of GL Analyser of Fusion Based Email Classification. [Citation Graph (, )][DBLP]
    
    
16. 
    Medical image classfication using an efficient data mining technique. [Citation Graph (, )][DBLP]
    
    
17. 
    A comparative study among three algorithms for frequent pattern generation. [Citation Graph (, )][DBLP]
    
    
18. 
    Multi-classifier Classification of Spam Email on a Ubiquitous Multi-core Architecture. [Citation Graph (, )][DBLP]
    
    
19. 
    Email Categorization Using Multi-stage Classification Technique. [Citation Graph (, )][DBLP]
    
    
20. 
    Spam filtering for network traffic security on a multi-core environment. [Citation Graph (, )][DBLP]
    
    
21. 
    Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings [Citation Graph (, )][DBLP]
    
    
22. 
    Efficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing [Citation Graph (, )][DBLP]
    
    
23. 
    Variable Block Carry Skip Logic using Reversible Gates [Citation Graph (, )][DBLP]
    
    
24. 
    Sorting Network for Reversible Logic Synthesis [Citation Graph (, )][DBLP]
    
    
25. 
    Machine Learning Approaches for Modeling Spammer Behavior [Citation Graph (, )][DBLP]
    
    
26. 
    Wrapper/TAM Co-Optimization and Test Scheduling for SOCs Using Rectangle Bin Packing Considering Diagonal Length of Rectangles [Citation Graph (, )][DBLP]
    
    
27. 
    Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing [Citation Graph (, )][DBLP]