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Vikram Iyengar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:320-0 [Conf]
  2. Vikram Iyengar, Phil Nigh
    Defect-Oriented Test for Ultra-Low DPM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:455- [Conf]
  3. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:685-690 [Conf]
  4. Vikram Iyengar, Gary Grise, Mark Taylor
    A flexible and scalable methodology for GHz-speed structural test. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:314-319 [Conf]
  5. Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
    Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:738-743 [Conf]
  6. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient Wrapper/TAM Co-Optimization for Large SOCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:491-498 [Conf]
  7. Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty
    A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11188-11190 [Conf]
  8. Chunsheng Liu, Vikram Iyengar
    Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:652-657 [Conf]
  9. Vikram Iyengar, Anshuman Chandra
    A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:511-518 [Conf]
  10. Chunsheng Liu, Kugesh Veeraraghavant, Vikram Iyengar
    Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:552-562 [Conf]
  11. Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich
    Performance verification of high-performance ASICs using at-speed structural test. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:247-252 [Conf]
  12. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Test wrapper and test access mechanism co-optimization for system-on-chip. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1023-1032 [Conf]
  13. Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1159-1168 [Conf]
  14. Sandeep Koranne, Vikram Iyengar
    On the Use of k-tuples for SoC Test Schedule Representation. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:539-548 [Conf]
  15. Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty
    A Set of Benchmarks fo Modular Testing of SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:519-528 [Conf]
  16. Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara
    Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  17. Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
    Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:22-27 [Conf]
  18. Vikram Iyengar, Krishnendu Chakrabarty
    Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:368-374 [Conf]
  19. Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar
    Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:299-312 [Conf]
  20. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:253-258 [Conf]
  21. Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray
    Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:418-423 [Conf]
  22. Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan
    Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:46-51 [Conf]
  23. Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota
    Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:349-354 [Conf]
  24. Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland
    An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:173-178 [Conf]
  25. Vikram Iyengar, Krishnendu Chakrabarty
    An Efficient Finite-State Machine Implementation of Huffman Decoders. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1997, v:64, n:6, pp:271-275 [Journal]
  26. Vikram Iyengar, Krishnendu Chakrabarty
    Test Bus Sizing for System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:5, pp:449-459 [Journal]
  27. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:12, pp:1619-1632 [Journal]
  28. Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski
    Test planning for modular testing of hierarchical SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:435-448 [Journal]
  29. Vikram Iyengar, Krishnendu Chakrabarty
    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1088-1094 [Journal]
  30. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient test access mechanism optimization for system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:635-643 [Journal]
  31. Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
    SOC test planning using virtual test access architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1263-1276 [Journal]
  32. Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar
    Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:633-636 [Journal]

  33. AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. [Citation Graph (, )][DBLP]


  34. Variation-aware performance verification using at-speed structural test and statistical timing. [Citation Graph (, )][DBLP]


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