The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Erik Jan Marinissen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:320-0 [Conf]
  2. Tom Waayers, Erik Jan Marinissen, Maurice Lousberg
    IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:450- [Conf]
  3. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:685-690 [Conf]
  4. Yervant Zorian, Erik Jan Marinissen
    System chip test: how will it impact your design? [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:136-141 [Conf]
  5. Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk
    Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:108-113 [Conf]
  6. Sandeep Kumar Goel, Erik Jan Marinissen
    Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10738-10741 [Conf]
  7. Sandeep Kumar Goel, Erik Jan Marinissen
    On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:44-49 [Conf]
  8. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient Wrapper/TAM Co-Optimization for Large SOCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:491-498 [Conf]
  9. Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian
    Challenges in Embedded Memory Design and Test. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:722-727 [Conf]
  10. Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller
    Creating Value Through Test. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10402-10409 [Conf]
  11. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:285-290 [Conf]
  12. Erik Jan Marinissen
    An Industrial Approach to Core-Based System Chip Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:389-400 [Conf]
  13. Joep Aerts, Erik Jan Marinissen
    Scan chain design for test time reduction in core-based ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:448-457 [Conf]
  14. Sandeep Kumar Goel, Erik Jan Marinissen
    Effective and Efficient Test Architecture Design for SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:529-538 [Conf]
  15. Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
    Optimal Interconnect ATPG Under a Ground-Bounce Constraint. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:369-378 [Conf]
  16. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Test wrapper and test access mechanism co-optimization for system-on-chip. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1023-1032 [Conf]
  17. Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1159-1168 [Conf]
  18. Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
    Application of deterministic logic BIST on industrial circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:105-114 [Conf]
  19. Erik Jan Marinissen
    Security vs. Test Quality: Can We Really Only Have One at a Time? [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1411- [Conf]
  20. Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters
    A structured and scalable mechanism for test access to embedded reusable cores. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:284-293 [Conf]
  21. Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty
    A Set of Benchmarks fo Modular Testing of SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:519-528 [Conf]
  22. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1203-1212 [Conf]
  23. Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge
    Trends in Testing Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:688-697 [Conf]
  24. Yervant Zorian, Erik Jan Marinissen, Sujit Dey
    Testing embedded-core based system chips. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:130-0 [Conf]
  25. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur
    On using IEEE P1500 SECT for test plug-n-play. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:770-777 [Conf]
  26. Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
    Towards a standard for embedded core test: an example. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:616-627 [Conf]
  27. Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel
    Wrapper design for embedded core test. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:911-920 [Conf]
  28. Sandeep Kumar Goel, Erik Jan Marinissen
    Cluster-Based Test Architecture Design for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:259-264 [Conf]
  29. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:253-258 [Conf]
  30. Yervant Zorian, Erik Jan Marinissen, Sujit Dey
    Testing Embedded-Core-Based System Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:6, pp:52-60 [Journal]
  31. Krishnendu Chakrabarty, Erik Jan Marinissen
    How Useful are the ITC 02 SoC Test Benchmarks? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:120- [Journal]
  32. Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts
    Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:8-18 [Journal]
  33. Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:262-265 [Journal]
  34. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:12, pp:1619-1632 [Journal]
  35. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient test access mechanism optimization for system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:635-643 [Journal]
  36. Sandeep Kumar Goel, Erik Jan Marinissen
    SOC test architecture design for efficient utilization of test bandwidth. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:399-429 [Journal]
  37. Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson, Clemens Wouters
    Test quality analysis and improvement for an embedded asynchronous FIFO. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:859-864 [Conf]
  38. Paul Wielage, Erik Jan Marinissen, Michel Altheimer, Clemens Wouters
    Design and DfT of a high-speed area-efficient embedded asynchronous FIFO. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:853-858 [Conf]
  39. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
    Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:213-218 [Conf]
  40. Sandeep Kumar Goel, Erik Jan Marinissen
    On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  41. Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
    Optimal Interconnect ATPG Under a Ground-Bounce Constraint. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:17-31 [Journal]

  42. On Scan Chain Diagnosis for Intermittent Faults. [Citation Graph (, )][DBLP]


  43. Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. [Citation Graph (, )][DBLP]


  44. Contactless testing: Possibility or pipe-dream? [Citation Graph (, )][DBLP]


  45. Testing TSV-based three-dimensional stacked ICs. [Citation Graph (, )][DBLP]


  46. Adapting to adaptive testing. [Citation Graph (, )][DBLP]


  47. Test-architecture optimization for TSV-based 3D stacked ICs. [Citation Graph (, )][DBLP]


  48. On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. [Citation Graph (, )][DBLP]


  49. Impact of 3D design choices on manufacturing cost. [Citation Graph (, )][DBLP]


  50. DATE 07 workshop on diagnostic services in NoCs. [Citation Graph (, )][DBLP]


  51. Bugs, moths, grasshoppers, and whales. [Citation Graph (, )][DBLP]


  52. Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis. [Citation Graph (, )][DBLP]


  53. Guest Editors' Introduction: The Status of IEEE Std 1500. [Citation Graph (, )][DBLP]


  54. IEEE Std 1500 Enables Modular SoC Testing. [Citation Graph (, )][DBLP]


  55. Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2. [Citation Graph (, )][DBLP]


  56. Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. [Citation Graph (, )][DBLP]


Search in 0.008secs, Finished in 0.011secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002