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Debashis Sahoo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu
Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 2005, pp:460- [Conf] - Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill
A New Reachability Algorithm for Symmetric Multi-processor Architecture. [Citation Graph (0, 0)][DBLP]
ATVA, 2005, pp:26-38 [Conf] - Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle
Error Detection Using BMC in a Parallel Environment. [Citation Graph (0, 0)][DBLP]
CHARME, 2005, pp:354-358 [Conf] - Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain
Improved Symbolic Verification Using Partitioning Techniques. [Citation Graph (0, 0)][DBLP]
CHARME, 2003, pp:410-424 [Conf] - Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
Predictive Reachability Using a Sample-Based Approach. [Citation Graph (0, 0)][DBLP]
CHARME, 2005, pp:388-392 [Conf] - Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
Multi-threaded reachability. [Citation Graph (0, 0)][DBLP]
DAC, 2005, pp:467-470 [Conf] - Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
On Partitioning and Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
FM, 2005, pp:497-511 [Conf] - Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
A Partitioning Methodology for BDD-Based Verification. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:399-413 [Conf] - Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, E. Allen Emerson
Under-approximation Heuristics for Grid-based Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
Electr. Notes Theor. Comput. Sci., 2006, v:135, n:2, pp:31-46 [Journal] - Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
On partitioning and symbolic model checking. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:780-788 [Journal]
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