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Raimund Ubar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:318-325 [Conf]
  2. Adam Morawiec, Raimund Ubar, Jaan Raik
    Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:743- [Conf]
  3. Jaan Raik, Raimund Ubar
    Sequential Circuit Test Generation Using Decision Diagram Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:736-740 [Conf]
  4. André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová
    Internet-Based Collaborative Test Generation with MOSCITO. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:221-226 [Conf]
  5. Raimund Ubar, Artur Jutman, Zebo Peng
    Timing simulation of digital circuits with binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:460-466 [Conf]
  6. Raimund Ubar, Jaan Raik, Adam Morawiec
    Cycle-based Simulation with Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:454-458 [Conf]
  7. Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
    Layout to Logic Defect Analysis for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:35-40 [Conf]
  8. Raimund Ubar, Maksim Jenihhin
    Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:3-8 [Conf]
  9. Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik
    Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:86-91 [Conf]
  10. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
    Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:212-217 [Conf]
  11. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:225-0 [Conf]
  12. Gert Jervan, Zebo Peng, Raimund Ubar
    Test Cost Minimization for Hybrid Bist. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:283-291 [Conf]
  13. Vladimir Hahanov, Raimund Ubar, Stanley Hyduke
    Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:370-377 [Conf]
  14. Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov
    An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:412-419 [Conf]
  15. Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng
    Fast Test Cost Calculation for Hybrid BIST in Digital Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:318-325 [Conf]
  16. Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar
    Improved Fault Emulation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:72-78 [Conf]
  17. André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
    Integrated Design and Test Generation Under Internet Based Environment MOSCITO. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:187-195 [Conf]
  18. Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
    Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:79-82 [Conf]
  19. Jaan Raik, Raimund Ubar, Taavi Viilukas
    High-Level Decision Diagram based Fault Models for Targeting FSMs. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:353-358 [Conf]
  20. Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
    Off-Line Testing of Delay Faults in NoC Interconnects. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:677-680 [Conf]
  21. Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman
    Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. [Citation Graph (0, 0)][DBLP]
    EDCC, 2005, pp:332-344 [Conf]
  22. Raimund Ubar
    Test Generation for Digital Systems Based on Alternative Graphs. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:151-164 [Conf]
  23. Raimund Ubar, Marina Brik
    Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:264-282 [Conf]
  24. Raimund Ubar, Dominique Borrione
    Design Error Diagnosis in Digital Circuits without Error Model. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:281-292 [Conf]
  25. Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider
    Web-Based Environment for Digital Electronics Test Tools. [Citation Graph (0, 0)][DBLP]
    Virtual Enterprises and Collaborative Networks, 2004, pp:435-442 [Conf]
  26. Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
    A Hybrid BIST Architecture and Its Optimization for SoC Testing. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:273-279 [Conf]
  27. Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:365-371 [Conf]
  28. Raimund Ubar, Jaan Raik
    Efficient Hierarchical Approach to Test Generation for Digital Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:189-196 [Conf]
  29. Vladimir Hahanov, Raimund Ubar
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:103-0 [Journal]
  30. Vladimir Hahanov, Raimund Ubar, Subhasish Mitra
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:594-595 [Journal]
  31. Raimund Ubar
    Test Synthesis with Alternative Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:1, pp:48-57 [Journal]
  32. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Test Time Minimization for Hybrid BIST of Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:907-912 [Journal]
  33. Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:12, pp:2023-2040 [Journal]
  34. T. Cibáková, M. Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Hierarchical test generation for combinational circuits with real defects coverage. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:7, pp:1141-1149 [Journal]
  35. Jaan Raik, Raimund Ubar, Vineeth Govind
    Test Configurations for Diagnosing Faulty Links in NoC Switches. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:29-34 [Conf]
  36. Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
    Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:131-136 [Conf]
  37. Jaan Raik, Tanel Nõmmeots, Raimund Ubar
    A New Testability Calculation Method to Guide RTL Test Generation. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:71-82 [Journal]

  38. Parallel fault backtracing for calculation of fault coverage. [Citation Graph (, )][DBLP]


  39. A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. [Citation Graph (, )][DBLP]


  40. Parallel X-fault simulation with critical path tracing technique. [Citation Graph (, )][DBLP]


  41. Calculation of LFSR Seed and Polynomial Pair for BIST Applications. [Citation Graph (, )][DBLP]


  42. Code Coverage Analysis using High-Level Decision Diagrams. [Citation Graph (, )][DBLP]


  43. Web-Based Framework for Parallel Distributed Test. [Citation Graph (, )][DBLP]


  44. Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. [Citation Graph (, )][DBLP]


  45. Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. [Citation Graph (, )][DBLP]


  46. Fault Diagnosis in Integrated Circuits with BIST. [Citation Graph (, )][DBLP]


  47. Hierarchical Identification of Untestable Faults in Sequential Circuits. [Citation Graph (, )][DBLP]


  48. Hybrid BIST Optimization Using Reseeding and Test Set Compaction. [Citation Graph (, )][DBLP]


  49. Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. [Citation Graph (, )][DBLP]


  50. Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. [Citation Graph (, )][DBLP]


  51. Structural fault collapsing by superposition of BDDs for test generation in digital circuits. [Citation Graph (, )][DBLP]


  52. Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. [Citation Graph (, )][DBLP]


  53. Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. [Citation Graph (, )][DBLP]


  54. Evolutionary Approach to Test Generation for Functional BIST [Citation Graph (, )][DBLP]


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