Arabi Keshk, Yukiya Miura, Kozo Kinoshita Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2000, pp:120-124 [Conf]
Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP