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Piet Engelke: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
    On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:266-271 [Conf]
  2. Ilia Polian, Piet Engelke, Bernd Becker
    Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:216-0 [Conf]
  3. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1051-1059 [Conf]
  4. Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
    X-Masking During Logic BIST and Its Impact on Defect Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:442-451 [Conf]
  5. Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
    The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:171-178 [Conf]
  6. Ilia Polian, Sandip Kundu, Jean Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
    Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:343-348 [Conf]
  7. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Simulating Resistive-Bridging and Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2181-2192 [Journal]
  8. Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
    X-masking during logic BIST and its impact on defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:193-202 [Journal]
  9. Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
    Modeling Feedback Bridging Faults with Non-Zero Resistance. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:57-69 [Journal]
  10. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
    Automatic Test Pattern Generation for Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:61-69 [Journal]

  11. Dynamic Compaction in SAT-Based ATPG. [Citation Graph (, )][DBLP]


  12. Resistive Bridging Fault Simulation of Industrial Circuits. [Citation Graph (, )][DBLP]


  13. Diagnosis of Realistic Defects Based on the X-Fault Model. [Citation Graph (, )][DBLP]


  14. TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. [Citation Graph (, )][DBLP]


  15. Automatic Test Pattern Generation for Interconnect Open Defects. [Citation Graph (, )][DBLP]


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