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Publications of Author

1. Kuen-Jong Lee, Jih-Jeen Chen
   Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2002, pp:338-0 [Conf]
   
2. Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen
   Peak-power reduction for multiple-scan circuits during test application. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:453-458 [Conf]
   
3. Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
   Using a single input to support multiple scan chains. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:74-78 [Conf]
   
4. Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee
   Test pattern generation and clock disabling for simultaneous test time and power reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:363-370 [Journal]
   
5. Kuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang
   Broadcasting test patterns to multiple circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1793-1802 [Journal]