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Jing-Jou Tang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Kuen-Jong Lee, Jing-Jou Tang
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1996, pp:165-171 [Conf] - Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1998, pp:113-118 [Conf] - Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1996, pp:100-0 [Conf] - Jing-Jou Tang
An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1999, pp:81-0 [Conf] - Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). [Citation Graph (0, 0)][DBLP]
ISCAS, 1995, pp:393-396 [Conf] - Li-Chun Tien, Jing-Jou Tang, Mi-Chang Chang
An Automatic Layout Generator for I/O Cells. [Citation Graph (0, 0)][DBLP]
IWSOC, 2005, pp:295-300 [Conf] - Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
A graph representation for programmable logic arrays to facilitate testing and logic design. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1030-1043 [Journal] - Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. [Citation Graph (0, 0)][DBLP]
ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:2, pp:194-218 [Journal] - Tzyy-Kuen Tien, Jing-Jou Tang, Kuan-Jou Chen
A new high speed dynamic PLA. [Citation Graph (0, 0)][DBLP]
ISCAS, 2006, pp:- [Conf] - Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu
A practical current sensing technique for IDDQ testing. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:302-310 [Journal]
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