The SCEAS System
Navigation Menu

Search the dblp DataBase


Rafic Z. Makki: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jian Liu, Rafic Z. Makki, Ayman I. Kayssi
    Dynamic Power Supply Current Testing of SRAMs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:348-353 [Conf]
  2. Rafic Z. Makki
    Testing of Embedded Memories - The Aggregate. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:519- [Conf]
  3. Jian Liu, Rafic Z. Makki
    Power supply current detectability of SRAM defects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:367-0 [Conf]
  4. Suriya Ashok Kumar, Rafic Z. Makki, David Binkley
    IDDT Testing of Embedded CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1117- [Conf]
  5. Ali Chehab, Rafic Z. Makki, Michael Spica, David Wu
    IDDT Test Methodologies for Very Deep Sub-micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:403-407 [Conf]
  6. Scott Thomas, Rafic Z. Makki, Sai Kishore Vavilala
    Measurement and Analysis of Physical Defects for Dynamic Supply Current Testing. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:195-202 [Conf]
  7. Rafic Z. Makki, Kasra Daneshvar, Farid Tranjan, Richard Greene
    On the Integration of Design and Manufacturing for Improved Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:248-255 [Conf]
  8. Rafic Z. Makki, Shyang-Tai Su, Troy Nagle
    Transient Power Supply Current Testing of Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:892-901 [Conf]
  9. Rafic Z. Makki, C. Tiansheng
    Designing Testable Control Paths with Multiple and Feedback Scan-Paths. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:484-492 [Conf]
  10. Rafic Z. Makki, Silvio Bou-Ghazale, Chen Tianshang
    Automatic Test Pattern Generation with Branch Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:785-791 [Journal]
  11. Ali Chehab, Saurabh Patel, Rafic Z. Makki
    Scaling of iDDT Test Methods for Random Logic Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:11-22 [Journal]

  12. On Wires Holding a Handful of Electrons. [Citation Graph (, )][DBLP]

Search in 0.004secs, Finished in 0.005secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002