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Shyue-Kung Lu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shyue-Kung Lu, Chung-Yang Chen
    Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:236-241 [Conf]
  2. Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
    Defect Level Prediction Using Multi-Model Fault Coverage. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:301-0 [Conf]
  3. Shyue-Kung Lu, Jeh-Sheng Shih, Cheng-Wen Wu
    A Testable/Fault Tolerant FFT Processor Design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:429-0 [Conf]
  4. Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai
    Testing and Diagnosis Techniques for LUT-Based FPGA's. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:414-419 [Conf]
  5. Shyue-Kung Lu, Chien-Hung Yeh
    Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:230-0 [Conf]
  6. Shyue-Kung Lu, Mau-Jung Lu
    Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:416-418 [Conf]
  7. Cheng-Wen Wu, Shyue-Kung Lu
    Designing Self-Testable Cellular Arrays. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:110-113 [Conf]
  8. Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang
    Combinational circuit fault diagnosis using logic emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:549-552 [Conf]
  9. Shyue-Kung Lu, Chih-Hsien Hsu
    Built-In self-repair for divided word line memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:13-16 [Conf]
  10. Shyue-Kung Lu, Cheng-Wen Wu
    A novel approach to testing LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:173-177 [Conf]
  11. Shyue-Kung Lu, Shih-Chang Huang
    Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:60-64 [Conf]
  12. Shyue-Kung Lu, Chien-Hung Yeh
    Enhancing Delay Fault Testability for Iterative Logic Array. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:283-292 [Conf]
  13. Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin
    Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors. [Citation Graph (0, 0)][DBLP]
    PRDC, 2004, pp:321-326 [Conf]
  14. Chih-Hsien Hsu, Shyue-Kung Lu, Sy-Yen Kuo
    Novel Fault-Tolerant Techniques for High Capacity RAMs. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:11-18 [Conf]
  15. Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu
    Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits. [Citation Graph (0, 0)][DBLP]
    PRDC, 2006, pp:97-104 [Conf]
  16. Ming-Wei Wu, Yennun Huang, Shyue-Kung Lu, Ing-Yi Chen, Sy-Yen Kuo
    A Multi-Faceted Approach towards Spam-Resistible Mail. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:208-218 [Conf]
  17. Ming-Wei Wu, Yennun Huang, Ing-Yi Chen, Shyue-Kung Lu, Sy-Yen Kuo
    A Scalable Port Forwarding for P2P-Based Wi-Fi Applications. [Citation Graph (0, 0)][DBLP]
    WASA, 2006, pp:26-37 [Conf]
  18. Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu
    Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:4, pp:571-587 [Journal]
  19. Shyue-Kung Lu, Jen-Sheng Shih
    Testing Configurable LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:733-750 [Journal]
  20. Shyue-Kung Lu, Sy-Yen Kuo, Cheng-Wen Wu
    Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:9, pp:1028-1034 [Journal]
  21. Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang
    Design-for-testability and fault-tolerant techniques for FFT processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:732-741 [Journal]
  22. Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
    Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:34-42 [Journal]
  23. Shyue-Kung Lu, Chih-Hsien Hsu
    Fault tolerance techniques for high capacity RAM. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2006, v:55, n:2, pp:293-306 [Journal]
  24. Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu
    C-testable design techniques for iterative logic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:146-152 [Journal]

  25. Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. [Citation Graph (, )][DBLP]


  26. Built-In Self-Repair Techniques for Heterogeneous Memory Cores. [Citation Graph (, )][DBLP]


  27. Fault-tolerance design of memory systems based on DBL structures. [Citation Graph (, )][DBLP]


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