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J. Th. van der Linden: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor
    Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:29-33 [Conf]
  2. J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor
    Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:212-0 [Conf]
  3. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Illegal State Space Identification for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:741-746 [Conf]
  4. M. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor
    Test point insertion for compact test sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:292-301 [Conf]
  5. M. J. Geuzebroek, J. Th. van der Linden, A. J. van de Goor
    Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:138-147 [Conf]
  6. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Test Pattern Generation with Restrictors. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:598-605 [Conf]
  7. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Accelerated Compact Test Set Generation for Three-State Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:29-38 [Conf]
  8. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Sequential Test Generation with Advanced Illegal State Search. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:733-742 [Conf]
  9. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Testability of the Philips 80C51 micro-controller. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:820-829 [Conf]
  10. J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor
    Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:604-613 [Conf]
  11. M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor
    Compact test sets for industrial circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:358-366 [Conf]

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