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David C. Keezer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. A. M. Majid, David C. Keezer, J. V. Karia
    A 5 Gbps Wafer-Level Tester. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:58-63 [Conf]
  2. David C. Keezer, C. Gray, A. M. Majid, N. Taher
    Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:152-157 [Conf]
  3. N. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer
    SMAC: A Scene Matching Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:184-187 [Conf]
  4. S. P. Athan, David C. Keezer, J. McKinley
    High Frequency Wafer Probing and Power Supply Resonance Effects. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:1069-1078 [Conf]
  5. J. S. Davis, David C. Keezer
    Multi-Purpose Digital Test Core Utilizing Programmable Logic. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:438-445 [Conf]
  6. J. S. Davis, David C. Keezer, O. Liboiron-Ladouceur, K. Bergman
    Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:166-174 [Conf]
  7. L. J. Falkenstrom, David C. Keezer, A. Patterson, Robert M. Rolfe, J. Wolcott
    Tester Independent Support Software System (TISSS). [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:685-691 [Conf]
  8. David C. Keezer
    GHz Testing and Its Fuzzy Targets. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1230- [Conf]
  9. David C. Keezer
    Real-Time Data Comparison for GigaHertz Digital Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:790-797 [Conf]
  10. David C. Keezer
    MCM Test Using Available Technology. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:253- [Conf]
  11. David C. Keezer
    Known Godd Die for MCMs: Enabling Technologies. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:266- [Conf]
  12. David C. Keezer
    Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:917- [Conf]
  13. David C. Keezer, Dany Minier, F. Binette
    Modular Extension of ATE to 5 Gbps. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:748-757 [Conf]
  14. David C. Keezer, Dany Minier, Marie-Christine Caron
    A Production-Oriented Multiplexing System for Testing above 2.5 Gbps. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:191-200 [Conf]
  15. David C. Keezer, K. E. Newman, J. S. Davis
    Improved sensitivity for parallel test of substrate interconnections. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:228-233 [Conf]
  16. David C. Keezer, R. J. Wenzel
    Calibration Techniques for a Gigahertz Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:530-537 [Conf]
  17. David C. Keezer, R. J. Wenzel
    Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:94-100 [Conf]
  18. David C. Keezer, Q. Zhou
    Alternative interface methods for testing high speed bidirectional signals. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:824-830 [Conf]
  19. David C. Keezer, Q. Zhou
    Test support processors for enhanced testability of high performance circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:801-809 [Conf]
  20. David C. Keezer, Q. Zhou, C. Bair, J. Kuan, B. Poole
    Terabit-per-second automated digital testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1143-1189 [Conf]
  21. Bruce C. Kim, David C. Keezer, Abhijit Chatterjee
    A high throughput test methodology for MCM substrates. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:234-0 [Conf]
  22. K. E. Newman, David C. Keezer
    A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:370-378 [Conf]
  23. Karim Arabi, Klaus-Dieter Hilliges, David C. Keezer, Sassan Tabatabaei
    Multi-GigaHertz Testing Challenges and Solutions. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:265-268 [Conf]
  24. Vijay K. Jain, Hiroomi Hikawa, David C. Keezer
    An Architecture for WSI Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:4, pp:71-75 [Journal]
  25. David C. Keezer, Dany Minier, Marie-Christine Caron
    Multiplexing ATE Channels for Production Testing at 2.5 Gbps. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:4, pp:288-301 [Journal]
  26. David C. Keezer, Dany Minier, Patrice Ducharme
    Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:1, pp:46-57 [Journal]
  27. David C. Keezer, Dany Minier, Patrice Ducharme
    Method for reducing jitter in multi-gigahertz ATE. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:701-706 [Conf]
  28. David C. Keezer, C. Gray, A. M. Majid, N. Taher
    Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  29. Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications. [Citation Graph (, )][DBLP]

  30. Stretching the limits of FPGA SerDes for enhanced ATE performance. [Citation Graph (, )][DBLP]

  31. An architecture for graphics processing in an FPGA (abstract only). [Citation Graph (, )][DBLP]

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