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T. M. Mak: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. T. M. Mak
    Limitation of structural scan delay test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:471- [Conf]
  2. Cecilia Metra, T. M. Mak, Martin Omaña
    Fault secureness need for next generation high performance microprocessor design for testability structures. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:444-450 [Conf]
  3. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
    Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:668-673 [Conf]
  4. Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir
    On path-based learning and its applications in delay test and diagnosis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:492-497 [Conf]
  5. Cecilia Metra, T. M. Mak, Martin Omaña
    Are Our Design for Testability Features Fault Secure? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:714-715 [Conf]
  6. Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak
    Can Clock Faults be Detected Through Functional Test? [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:168-173 [Conf]
  7. Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak
    Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:357-365 [Conf]
  8. Cecilia Metra, T. M. Mak, Daniele Rossi
    Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:63-70 [Conf]
  9. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    The Other Side of the Timing Equation: a Result of Clock Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:169-177 [Conf]
  10. Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng
    A path-based methodology for post-silicon timing validation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:713-720 [Conf]
  11. T. M. Mak
    Does It Mean Less Testing for Self Calibrating Design?. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:99- [Conf]
  12. T. M. Mak
    Test Challenges for 3D Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:79- [Conf]
  13. T. M. Mak, Subhasish Mitra, Ming Zhang
    DFT Assisted Built-In Soft Error Resilience. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:69- [Conf]
  14. Eric F. Weglarz, Kewal K. Saluja, T. M. Mak
    Testing of Hard Faults in Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:95-100 [Conf]
  15. T. M. Mak, Subhasish Mitra
    Should Logic SER be Solved at the Circuit Level? [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:199- [Conf]
  16. Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak
    Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:17-22 [Conf]
  17. Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
    Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:153-158 [Conf]
  18. Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
    Crosstalk test generation on pseudo industrial circuits: a case study. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:548-557 [Conf]
  19. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
    Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:339-348 [Conf]
  20. Sandip Kundu, T. M. Mak, Rajesh Galivanche
    Trends in manufacturing test methods and their implications. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:679-687 [Conf]
  21. T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, Joel Ferguson, Jianlin Yu
    Cache RAM inductive fault analysis with fab defect modeling. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:862-871 [Conf]
  22. Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
    Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:100-109 [Conf]
  23. Cecilia Metra, T. M. Mak, Martin Omaña
    Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1223-1231 [Conf]
  24. Mike Tripp, T. M. Mak, Anne Meixner
    Elimination of Traditional Functional Testing of Interface Timings at Intel. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1014-1022 [Conf]
  25. Mike Tripp, T. M. Mak, Anne Meixner
    Elimination of Traditional Functional Testing of Interface Timings at Intel. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1448-1456 [Conf]
  26. Michael Spica, T. M. Mak
    Do We Need Anything More Than Single Bit Error Correction (ECC)? [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:111-116 [Conf]
  27. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
    Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:606-612 [Conf]
  28. Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak
    On Silicon-Based Speed Path Identification. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:35-41 [Conf]
  29. Kaushik Roy, T. M. Mak, Kwang-Ting Cheng
    Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:313-318 [Conf]
  30. Cecilia Metra, Martin Omaña, T. M. Mak, S. Tam
    Novel Approach to Clock Fault Testing for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:441-446 [Conf]
  31. Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
    Defect and Error Tolerance in the Presence of Massive Numbers of Defects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:216-227 [Journal]
  32. T. M. Mak
    Is System in Package the Panacea for Integration? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:256- [Journal]
  33. T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
    New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:241-247 [Journal]
  34. T. M. Mak, Mike Tripp, Anne Meixner
    Testing Gbps Interfaces without a Gigahertz Tester. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:4, pp:278-286 [Journal]
  35. Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
    Test Consideration for Nanometer-Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:128-136 [Journal]
  36. Cecilia Metra, Stefano Di Francescantonio, T. M. Mak
    Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:5, pp:531-546 [Journal]
  37. Cecilia Metra, Daniele Rossi, T. M. Mak
    Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:3, pp:415-428 [Journal]
  38. T. M. Mak
    Infant Mortality--The Lesser Known Reliability Issue. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:122- [Conf]
  39. Ming Zhang, T. M. Mak, James Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu
    Design for Resilience to Soft Errors and Variations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:23-28 [Conf]
  40. Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim
    Soft Error Resilient System Design through Error Correction. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:332-337 [Conf]
  41. Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel
    Sequential Element Design With Built-In Soft Error Resilience. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1368-1378 [Journal]

  42. Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. [Citation Graph (, )][DBLP]


  43. Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. [Citation Graph (, )][DBLP]


  44. The case for power with test. [Citation Graph (, )][DBLP]


  45. Guest Editors' Introduction: Process Variation and Stochastic Design and Test. [Citation Graph (, )][DBLP]


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