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Chin-Long Wey: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shaolei Quan, Qiang Qiang, Chin-Long Wey
    Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:70-75 [Conf]
  2. Cheng-Ping Wang, Chin-Long Wey
    Test Generation Of Analog Switched-Current Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:276-281 [Conf]
  3. Chin-Long Wey, Meng-Yao Liu
    Burn-In Stress Test of Analog CMOS ICs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:360-365 [Conf]
  4. Chin-Long Wey, Adam Osseiran, José Luis Huertas, Yeon-Chen Nieu
    Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:15-0 [Conf]
  5. Chin-Long Wey
    On Yield Consideration for the Design of Redundant Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:622-628 [Conf]
  6. Chin-Long Wey, Tsin-Yuan Chang
    PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:421-426 [Conf]
  7. Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang
    Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:327-332 [Conf]
  8. Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
    An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:574-579 [Conf]
  9. Shaolei Quan, Meng-Yao Liu, Chin-Long Wey
    Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:563-572 [Conf]
  10. Manuel Jimenez, Chin-Long Wey, Michael A. Shanblatt
    Mapping Multiplication Algorithms into a Family of LUT-based FPGAs (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:259- [Conf]
  11. Shaolei Quan, Chin-Long Wey
    A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:178-182 [Conf]
  12. Chin-Long Wey, Mohammad Athar Khalil, Jim Liu, Gregory Wierzba
    Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:322-327 [Conf]
  13. Chin-Long Wey
    Concurrent Error Detection in Array Dividers by Alternating Input Data. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:114-117 [Conf]
  14. Chin-Long Wey
    Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:124-127 [Conf]
  15. Chin-Long Wey
    On Design of Efficient Square Generator. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:506-0 [Conf]
  16. Tzu-Hsi Pan, Hyon-Sok Kay, Youngsun Chun, Chin-Long Wey
    High-radix SRT division with speculation of quotient digits . [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:479-0 [Conf]
  17. Cheng-Ping Wang, Chin-Long Wey
    Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:468-473 [Conf]
  18. Chin-Long Wey, Ming-Der Shieh, P. David Fisher
    ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:159-162 [Conf]
  19. Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang
    A self-timed redundant-binary number to binary number converter for digital arithmetic processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:386-0 [Conf]
  20. Jun-Woo Kang, Chin-Long Wey, P. David Fisher
    Race-free state assignments using bipartite graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2560-2563 [Conf]
  21. Chin-Long Wey
    Built-In Self Test (BIST) Design of High-Speed Carry-Free Dividers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1916-1919 [Conf]
  22. Chin-Long Wey, Wei-Chien Tang, Shin-Yo Lin
    Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:98-106 [Conf]
  23. Mohammad Athar Khalil, Chin-Long Wey
    Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:348-357 [Conf]
  24. Shoba Krishnan, Sondes Sahli, Chin-Long Wey
    Test Generation and Concurrent Error Detection in Current-Mode A/D Converters. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:312-320 [Conf]
  25. Chin-Long Wey
    Fault Location in Repairable Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:679-685 [Conf]
  26. Fabrizio Lombardi, Chin-Long Wey
    On a Multiprocessor System with Dynamic Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1985, pp:3-12 [Conf]
  27. Mohammad Athar Khalil, Chin-Long Wey
    High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:333-338 [Conf]
  28. Chin-Long Wey, Fabrizio Lombardi
    On a Novel Self-Test Approach to Digital Testing. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1987, v:30, n:3, pp:258-267 [Journal]
  29. Jun-Woo Kang, Chin-Long Wey, P. David Fisher
    Application of Bipartite Graphs for Achieving Race-Free State Assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:8, pp:1002-1011 [Journal]
  30. Chin-Long Wey, Ming-Der Shieh
    Design of a High-Speed Square Generator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:9, pp:1021-1026 [Journal]
  31. Shek-Wayne Chan, Chin-Long Wey
    The design of concurrent error diagnosable systolic arrays for band matrix multiplications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:21-37 [Journal]
  32. Chin-Long Wey
    On yield consideration for the design of redundant programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:528-535 [Journal]
  33. Chin-Long Wey, Tsin-Yuan Chang
    An efficient output phase assignment for PLA minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:1, pp:1-7 [Journal]
  34. Chin-Long Wey, Shoba Krishnan, Sondes Sahli
    Test generation and concurrent error detection in current-mode A/D converters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1291-1298 [Journal]
  35. Chin-Long Wey, Fabrizio Lombardi
    On the Repair of Redundant RAM's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:2, pp:222-231 [Journal]
  36. Tsung-Han Tsai, Yung-Tsung Wang, Jui Hong Hung, Chin-Long Wey
    Compressed domain content-based retrieval of MP3 audio example using quantization tree indexing and melody-line tracking method. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  37. Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey
    An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  38. Chin-Long Wey
    Built-in self-test (BIST) design of high-speed carry-free dividers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:141-145 [Journal]

  39. A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing. [Citation Graph (, )][DBLP]


  40. PrSoC: Programmable System-on-chip (SoC) for silicon prototyping. [Citation Graph (, )][DBLP]


  41. Yield evaluation of analog placement with arbitrary capacitor ratio. [Citation Graph (, )][DBLP]


  42. Robustness investigation of the FlexRay system. [Citation Graph (, )][DBLP]


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