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Publications of Author

1. Jiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang
   An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2004, pp:82-87 [Conf]
   
2. Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma
   Reconfigurable multiple scan-chains for reducing test application time of SOCs. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:5846-5849 [Conf]
   
3. Jiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu
   A novel reseeding mechanism for pseudo-random testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2005, pp:2979-2982 [Conf]
   
4. Jiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang
   A don't-care based image circuit for function verification. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2002, pp:325-328 [Conf]
   
5. Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu
   A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1998, pp:322-330 [Conf]
   
6. Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin
   An Efficient Mechanism for Debugging RTL Description. [Citation Graph (0, 0)][DBLP]
   IWSOC, 2003, pp:370-373 [Conf]
   
7. Jiann-Chyi Rau, Kuo-Chun Kuo
   An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
   IWSOC, 2003, pp:374-377 [Conf]
   
8. Shih-Chieh Chang, Jiann-Chyi Rau
   A timing-driven pseudoexhaustive testing for VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:147-158 [Journal]
   
9. Jiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen
   A broadcast-based test scheme for reducing test size and application time. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
10. 
    New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology. [Citation Graph (, )][DBLP]
    
    
11. 
    Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs. [Citation Graph (, )][DBLP]
    
    
12. 
    A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits. [Citation Graph (, )][DBLP]
    
    
13. 
    An efficient test-data compaction for low power VLSI testing. [Citation Graph (, )][DBLP]