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Valentin Muresan:
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Publications of Author
- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2000, pp:465-470 [Conf]
- Andrew Kinane, Valentin Muresan, Noel E. O'Connor
Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP] EvoWorkshops, 2006, pp:296-307 [Conf]
- Andrew Kinane, Alan Casey, Valentin Muresan, Noel E. O'Connor
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator. [Citation Graph (0, 0)][DBLP] FPT, 2005, pp:317-318 [Conf]
- Daniel Larkin, Andrew Kinane, Valentin Muresan, Noel E. O'Connor
An Efficient Hardware Architecture for a Neural Network Activation Function Generator. [Citation Graph (0, 0)][DBLP] ISNN (2), 2006, pp:1319-1327 [Conf]
- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
A comparison of classical scheduling approaches in power-constrained block-test scheduling. [Citation Graph (0, 0)][DBLP] ITC, 2000, pp:882-891 [Conf]
- Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. [Citation Graph (0, 0)][DBLP] PATMOS, 2004, pp:780-788 [Conf]
- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Power-Constrained Block-Test List Scheduling. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2000, pp:182-187 [Conf]
- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2001, pp:162-167 [Conf]
- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. [Citation Graph (0, 0)][DBLP] VTS, 2000, pp:417-422 [Conf]
- Andrew Kinane, Valentin Muresan, Noel E. O'Connor
Towards an optimised VLSI design algorithm for the constant matrix multiplication problem. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
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