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Jean Michel Portal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 2000, pp:323-328 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1997, pp:254-0 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1998, pp:266-271 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
Minimizing the Number of Test Configurations for Different FPGA Families. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1999, pp:363-368 [Conf]
S. Bernardini, Jean Michel Portal, P. Masson
A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. [Citation Graph (0, 0)][DBLP]
DATE, 2004, pp:1404-1405 [Conf]
Laurent Lopez, Jean Michel Portal, Didier Née
A New Embedded Measurement Structure for eDRAM Capacitor. [Citation Graph (0, 0)][DBLP]
DATE, 2005, pp:462-463 [Conf]
Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, S. Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
Novel Technique for Testing FPGAs. [Citation Graph (0, 0)][DBLP]
DATE, 1998, pp:89-0 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
RAM-Based FPGA's: A Test Approach for the Configurable Logic. [Citation Graph (0, 0)][DBLP]
DATE, 1998, pp:82-88 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. [Citation Graph (0, 0)][DBLP]
DATE, 1999, pp:618-622 [Conf]
B. Saillet, Jean Michel Portal, Didier Née
Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. [Citation Graph (0, 0)][DBLP]
DFT, 2005, pp:131-139 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. [Citation Graph (0, 0)][DBLP]
FPL, 1998, pp:139-148 [Conf]
Anna Labbé, Annie Pérez, Jean Michel Portal
Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. [Citation Graph (0, 0)][DBLP]
ISCAS (2), 2004, pp:637-640 [Conf]
Jean Michel Portal, L. Forli, Didier Née
Floating-gate EEPROM cell: threshold voltage sensibility to geometry. [Citation Graph (0, 0)][DBLP]
ISCAS (1), 2002, pp:557-560 [Conf]
Jean Michel Portal, L. Forli, Didier Née
Floating-gate EEPROM cell model based on MOS model 9. [Citation Graph (0, 0)][DBLP]
ISCAS (3), 2002, pp:799-802 [Conf]
L. Forli, Jean Michel Portal, Didier Née, B. Borot
Infrastructure IP for Back-End Yield Improvement. [Citation Graph (0, 0)][DBLP]
ITC, 2003, pp:1129-1134 [Conf]
Jean Michel Portal, H. Aziza, Didier Née
EEPROM Memory: Threshold Voltage Built In Self Diagnosis. [Citation Graph (0, 0)][DBLP]
ITC, 2003, pp:23-28 [Conf]
Jean Michel Portal, L. Forli, H. Aziza, Didier Née
An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. [Citation Graph (0, 0)][DBLP]
ITC, 2002, pp:31-36 [Conf]
Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian
IS-FPGA : a new symmetric FPGA architecture with implicit scan. [Citation Graph (0, 0)][DBLP]
ITC, 2001, pp:924-931 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
SRAM-based FPGA's: testing the LUT/RAM modules. [Citation Graph (0, 0)][DBLP]
ITC, 1998, pp:1102-1111 [Conf]
Jean Michel Portal, L. Forli, H. Aziza, Didier Née
An Automated Design Methodology for EEPROM Cell (ADE). [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:137-142 [Conf]
Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
Testing the Interconnect of RAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 1998, v:15, n:1, pp:45-50 [Journal]
B. Saillet, A. Regnier, Jean Michel Portal, B. Delsuc, R. Laffont, P. Masson, R. Bouchakour
MM11 based flash memory cell model including characterization procedure. [Citation Graph (0, 0)][DBLP]
ISCAS, 2006, pp:- [Conf]
Laurent Lopez, Jean Michel Portal, Didier Née
A New Embedded Measurement Structure for eDRAM Capacitor [Citation Graph (0, 0)][DBLP]
CoRR, 2007, v:0, n:, pp:- [Journal]
Jean Michel Portal, H. Aziza, Didier Née
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. [Citation Graph (0, 0)][DBLP]
J. Electronic Testing, 2005, v:21, n:1, pp:33-42 [Journal]
An on-line testing scheme for repairing purposes in Flash memories. [Citation Graph (, )][DBLP]
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. [Citation Graph (, )][DBLP]
Metal filling impact on standard cells: definition of the metal fill corner concept. [Citation Graph (, )][DBLP]
Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. [Citation Graph (, )][DBLP]

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