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Joan Figueras: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
    TOF: a tool for test pattern generation optimization of an FPGA application oriented test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:323-328 [Conf]
  2. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:254-0 [Conf]
  3. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:266-271 [Conf]
  4. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Minimizing the Number of Test Configurations for Different FPGA Families. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:363-368 [Conf]
  5. Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, S. Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
    Novel Technique for Testing FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:89-0 [Conf]
  6. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    RAM-Based FPGA's: A Test Approach for the Configurable Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:82-88 [Conf]
  7. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:618-622 [Conf]
  8. Josep Rius, Joan Figueras
    Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:543-548 [Conf]
  9. Rosa Rodríguez-Montañés, Joan Figueras
    Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:490-494 [Conf]
  10. L. Balado, E. Lupon, L. García, Rosa Rodríguez-Montañés, Joan Figueras
    Lissajous Based Mixed-Signal Testing for N-Observable Signals. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:125-130 [Conf]
  11. Víctor H. Champac, Antonio Rubio, Joan Figueras
    Analysis of the Floating Gate Defect in CMOS. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:101-108 [Conf]
  12. Michel Renovell, Joan Figueras
    Current Testing Viability in Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:207-214 [Conf]
  13. Eugeni Isern, Joan Figueras
    Test of Bridging Faults in Scan-based Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:366-370 [Conf]
  14. Rosa Rodríguez-Montañés, Joan Figueras
    Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:356-360 [Conf]
  15. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:139-148 [Conf]
  16. Anna Maria Brosa, Joan Figueras
    On Optimizing Test Strategies for Analog Cells. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:92-96 [Conf]
  17. Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras
    Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:99-103 [Conf]
  18. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, M. Santos
    Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:110-113 [Conf]
  19. Anna Maria Brosa, Joan Figueras
    Digital signature proposal for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1041-1050 [Conf]
  20. Antoni Ferré, Joan Figueras
    IDDQ Characterization in Submicron CMOS. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:136-145 [Conf]
  21. Eugeni Isern, Joan Figueras
    Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:73-82 [Conf]
  22. Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian
    IS-FPGA : a new symmetric FPGA architecture with implicit scan. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:924-931 [Conf]
  23. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    SRAM-based FPGA's: testing the LUT/RAM modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1102-1111 [Conf]
  24. Rosa Rodríguez-Montañés, Joan Figueras, Eric Bruls
    Bridging Defects Resistance Measurements in a CMOS Process. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:892-899 [Conf]
  25. Rosa Rodríguez-Montañés, J. A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio
    Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:510-519 [Conf]
  26. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
    RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:814-823 [Conf]
  27. Yves Bertrand, Marie-Lise Flottes, L. Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, N. Pricopi, Hans-Joachim Wunderlich, J.-P. Van der Heyden
    Test Engineering Education in Europe: the EuNICE-Test Project. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:85-86 [Conf]
  28. Víctor H. Champac, Joan Figueras
    Testability of floating gate defects in sequential circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:202-207 [Conf]
  29. Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
    Power Dissipation During Testing: Should We Worry About it? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:456-457 [Conf]
  30. Víctor H. Champac, José Castillejos, Joan Figueras
    IDDQ Testing of Opens in CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:106-111 [Conf]
  31. Antoni Ferré, Joan Figueras
    On estimating bounds of the quiescent current for I/sub DDQ/ testin. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:106-111 [Conf]
  32. Salvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
    BIST Technique by Equally Spaced Test Vector Sequences. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:206-216 [Conf]
  33. Salvador Manich, Michael Nicolaidis, Joan Figueras
    Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:124-129 [Conf]
  34. Michel Renovell, Joan Figueras, Yervant Zorian
    Test of RAM-based FPGA: methodology and application to the interconnect. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:230-237 [Conf]
  35. Josep Rius, Joan Figueras
    Detecting I/sub DDQ/ defective CMOS circuits by depowering. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:324-329 [Conf]
  36. Rosa Rodríguez-Montañés, Joan Figueras
    Bridges in sequential CMOS circuits: current-voltage signatur. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:68-73 [Conf]
  37. D. Arumi, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:145-150 [Conf]
  38. Rosa Rodríguez-Montañés, D. Arumi, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Full Open Defects in Interconnecting Lines. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:158-166 [Conf]
  39. Eugeni Isern, Joan Figueras
    IDDQ Test and Diagnosis of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:4, pp:60-67 [Journal]
  40. Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras
    Fault-Secure Parity Prediction Arithmetic Operators. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:60-71 [Journal]
  41. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Interconnect of RAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:45-50 [Journal]
  42. Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
    IDDQ testing: state of the art and future trends. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:167-196 [Journal]
  43. Juan A. Carrasco, Joan Figueras, Annie Kuntzmann-Combelles
    Evaluation of safety-oriented two-version architectures. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 1991, v:14, n:3, pp:155-162 [Journal]
  44. Víctor H. Champac, Antonio Rubio, Joan Figueras
    Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:359-369 [Journal]
  45. Antoni Ferré, Joan Figueras
    Leakage power bounds in CMOS digital technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:731-738 [Journal]
  46. R. Sanahuja, V. Barcons, L. Balado, Joan Figueras
    Testing Biquad Filters under Parametric Shifts Using X-Y Zoning. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:257-265 [Journal]

  47. Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. [Citation Graph (, )][DBLP]


  48. Analog circuit test based on a digital signature. [Citation Graph (, )][DBLP]


  49. Data Dependence of Delay Distribution for a Planar Bus. [Citation Graph (, )][DBLP]


  50. Full Open Defects in Nanometric CMOS. [Citation Graph (, )][DBLP]


  51. Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. [Citation Graph (, )][DBLP]


  52. Diagnosis of full open defects in interconnect lines with fan-out. [Citation Graph (, )][DBLP]


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