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Jien-Chung Lo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tian Xia, Jien-Chung Lo
    On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:326-331 [Conf]
  2. Seok-Bum Ko, Tian Xia, Jien-Chung Lo
    Efficient Parity Prediction in FPGA. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:176-181 [Conf]
  3. Jien-Chung Lo
    Highly Reliable Systems with Differential Built-In Current Sensors. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:261-269 [Conf]
  4. Jien-Chung Lo, Eiji Fujiwara
    A Probabilistic Measurement for Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:263-270 [Conf]
  5. William D. Armitage, Jien-Chung Lo
    Erasure Error Correction with Hardware Detection. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:293-301 [Conf]
  6. Yu-Yau Guo, Jien-Chung Lo
    Challenges of Built-In Current Sensor Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:192-0 [Conf]
  7. Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra
    Fast and area-time efficient Berger code checkers. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:110-118 [Conf]
  8. Tian Xia, Jien-Chung Lo
    On-Chip Jitter Measurement for Phase Locked Loops. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:399-407 [Conf]
  9. Shengli Li, Kai Zhang, Jien-Chung Lo
    The 2nd Order Analysis of IDDQ Test Data. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:376-0 [Conf]
  10. Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara
    Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:120-130 [Conf]
  11. Chuen-Song Chen, Jien-Chung Lo, Tian Xia
    Equivalent IDDQ Tests for Systems with Regulated Power Supply. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:291-299 [Conf]
  12. Jien-Chung Lo, James C. Daly, Michael Nicolaidis
    Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:104-111 [Conf]
  13. Chuen-Song Chen, Jien-Chung Lo, Tian Xia
    An indirect current sensing technique for IDDQ and IDDT tests. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:235-240 [Conf]
  14. Seok-Bum Ko, Jien-Chung Lo
    Efficient Decomposition Techniques for FPGAs. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:630-642 [Conf]
  15. Jien-Chung Lo
    Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:110-113 [Conf]
  16. Jien-Chung Lo
    Fault-Tolerant Content Addressable Memory. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:193-196 [Conf]
  17. Seok-Bum Ko, Jien-Chung Lo
    A Novel Technology Mapping Method for AND/XOR Expressions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:133-138 [Conf]
  18. Jien-Chung Lo
    Online Current Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:49-56 [Journal]
  19. Jien-Chung Lo, William D. Armitage, Corbet S. Johnson
    Using Atomic Force Microscopy for Deep-Submicron Failure Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:10-18 [Journal]
  20. Tian Xia, Jien-Chung Lo
    On-chip short-time interval measurement system for high-speed signal timing characterization. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:4, pp:265-276 [Journal]
  21. Augustus K. Uht, Jien-Chung Lo, Ying Sun, James C. Daly, James Kowalski
    Building Real Computer Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:3, pp:48-56 [Journal]
  22. Jien-Chung Lo
    Analysis of a BICS-Only Concurrent Error Detection Method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:3, pp:241-253 [Journal]
  23. Jien-Chung Lo
    Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:400-412 [Journal]
  24. Jien-Chung Lo
    A Hyper Optimal Encoding Scheme for Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:9, pp:1022-1030 [Journal]
  25. Jien-Chung Lo
    A Fast Binary Adder with Conditional Carry Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:2, pp:248-253 [Journal]
  26. Jien-Chung Lo
    Correction to ``A Fast Binary Adder with Conditional Carry Generation'' IEEE Transaction on Computers 46(2) 248-253 (1997). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1425- [Journal]
  27. Jien-Chung Lo, Eiji Fujiwara
    Probability to Achieve TSC Goal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:450-460 [Journal]
  28. Jien-Chung Lo, Cecilia Metra, Fabrizio Lombardi
    Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:97-98 [Journal]
  29. Jien-Chung Lo, Suchai Thanawastien
    On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:387-393 [Journal]
  30. Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao
    Berger Check Prediction for Array Multipliers and Array Dividers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:7, pp:892-896 [Journal]
  31. Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao
    Berger Check Prediction for Array Multipliers and Array Dividers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:3, pp:383- [Journal]
  32. T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo
    Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:8, pp:1020-1024 [Journal]
  33. Jien-Chung Lo, James C. Daly, Michael Nicolaidis
    A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1402-1407 [Journal]
  34. Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao, Michael Nicolaidis
    An SFS Berger check prediction ALU and its application to self-checking processor designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:525-540 [Journal]

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