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Christian Steger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Klaus Rothbart, Ulrich Neffe, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger
    High Level Fault Injection for Attack Simulation in Smart Cards. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:118-121 [Conf]
  2. Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss
    A novel codesign approach based on distributed virtual machines. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:109-114 [Conf]
  3. Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger
    An Abstraction and Optimization Approach using HW/SW Co-design Techniques to get Power Aware Smart Card Solutions. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:137-143 [Conf]
  4. Christian Steger, Ulrich Neffe, Klaus Rothbart, Andreas Mühlberger, Edgar Rieger, Reinhold Weiss
    Methodologies for Designing Power-Aware Smart Card Systems. [Citation Graph (0, 0)][DBLP]
    Power-aware Computing Systems, 2005, pp:- [Conf]
  5. Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger
    Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:300-305 [Conf]
  6. Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss
    A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:212-219 [Conf]
  7. Christian Kreiner, Christian Steger, Reinhold Weiss
    WATIS2: Design and Application of an Environment Simulation System for Test Improvement of Control Software for Automatic Logistic Systems. [Citation Graph (0, 0)][DBLP]
    DS-RT, 2000, pp:5-12 [Conf]
  8. Klaus Rothbart, Ulrich Neffe, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger
    Power consumption profile analysis for security attack simulation in smart cards at high abstraction level. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:214-217 [Conf]
  9. Christian Kreiner, Christian Steger, Reinhold Weiss
    Improvement of Control Software for Automatic Logistic Systems Using Executable Environment Models. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:20919-20923 [Conf]
  10. Christian Kreiner, Christian Steger, Reinhold Weiss
    A Hardware/Software Cosimulation Environment for DSP Applications. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1492-1495 [Conf]
  11. M. Ruplitsch, Christian Steger, Reinhold Weiss
    A Hybrid Parallel Simulation System for Transputers. [Citation Graph (0, 0)][DBLP]
    EUROSIM, 1995, pp:273-278 [Conf]
  12. Mario Polaschegg, Christian Steger, Damian Dalton, Abhay Vadher
    Parallel Simulation with a Generic Simulation Framework Featuring Loose Coupling. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2005, pp:251-257 [Conf]
  13. Johannes Lauber, Christian Steger, Reinhold Weiss
    Autonomous Agents for Online Diagnosis of a Safety-critical System based on Probabilistic Causal Reasoning. [Citation Graph (0, 0)][DBLP]
    ISADS, 1999, pp:213-219 [Conf]
  14. Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton
    Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:290-291 [Conf]
  15. Klaus Rothbart, Ulrich Neffe, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger
    Extended abstract: an environment for design verification of smart card systems using attack simulation in SystemC. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:253-254 [Conf]
  16. Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger
    A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:491-500 [Conf]
  17. Alexander Maili, Damian Dalton, Christian Steger
    A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:799-808 [Conf]
  18. Christian Kreiner, Christian Steger, Reinhold Weiss
    Combining Different Models of Computation for Cosimulation of Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:751-757 [Conf]
  19. Johannes Lauber, Christian Steger, Reinhold Weiss
    Applied Probabilistic AI for Online Diagnosis of a Safety-Critical System Based on a Quality Assurance Program. [Citation Graph (0, 0)][DBLP]
    SAC, 1999, pp:25-30 [Conf]
  20. Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger
    Automated Software Power Optimization for Smart Card Systems with Focus on Peak Reduction. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:506-512 [Conf]
  21. Vojtech Derbek, Christian Steger, Reinhold Weiss, Daniel Wischounig, Josef Preishuber-Pfluegl, Markus Pistauer
    Simulation platform for UHF RFID. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:918-923 [Conf]
  22. Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger
    Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:268-277 [Conf]

  23. Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing. [Citation Graph (, )][DBLP]


  24. Compiler-based Software Power Peak Elimination on Smart Card Systems. [Citation Graph (, )][DBLP]


  25. 07041 Working Group - Towards Interfaces for Integrated Performance and Power Analysis and Simulation. [Citation Graph (, )][DBLP]


  26. Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors. [Citation Graph (, )][DBLP]


  27. Lifetime Extension of Higher Class UHF RFID Tags using special Power Management Techniques and Energy Harvesting Devices. [Citation Graph (, )][DBLP]


  28. Fault insertion testing of a novel CPLD-based fail-safe system. [Citation Graph (, )][DBLP]


  29. A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing. [Citation Graph (, )][DBLP]


  30. Holistic simulation of FlexRay networks by using run-time model switching. [Citation Graph (, )][DBLP]


  31. Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting Devices. [Citation Graph (, )][DBLP]


  32. Design and Implementation of Safety Functions on a Novel CPLD-Based Fail-Safe System Architecture. [Citation Graph (, )][DBLP]


  33. Rapid exploration of multimedia system-on-chips with automatically generated software performance models. [Citation Graph (, )][DBLP]


  34. Software Power Peak Reduction on Smart Card Systems Based on Iterative Compiling. [Citation Graph (, )][DBLP]


  35. Specification-based Verification of Embedded Systems by Automated Test Case Generation. [Citation Graph (, )][DBLP]


  36. TOSPIE2: tiny operating system plug-in for energy estimation. [Citation Graph (, )][DBLP]


  37. Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation. [Citation Graph (, )][DBLP]


  38. A system for accurate characterization of wireless sensor networks with power states and energy harvesting system efficiency. [Citation Graph (, )][DBLP]


  39. System level power profile analysis and optimization for smart cards and mobile devices. [Citation Graph (, )][DBLP]


  40. An emulation-based real-time power profiling unit for embedded software. [Citation Graph (, )][DBLP]


  41. Fast simulation based testing of anti-tearing mechanisms for small embedded systems. [Citation Graph (, )][DBLP]


  42. Verification and analysis of dependable automotive communication systems based on HW/SW co-simulation. [Citation Graph (, )][DBLP]


  43. Identification and Verification of Security Relevant Functions in Embedded Systems Based on Source Code Annotations and Assertions. [Citation Graph (, )][DBLP]


  44. SlimVM: a small footprint Java virtual machine for connected embedded systems. [Citation Graph (, )][DBLP]


  45. TEODACS : A new vision for testing dependable automotive communication systems. [Citation Graph (, )][DBLP]


  46. Automatic Generation of a Verification Platform. [Citation Graph (, )][DBLP]


  47. SystemC Based Design Space Exploration for Power Aware Smart Cards. [Citation Graph (, )][DBLP]


  48. A Generic Simulation Framework for Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  49. Java Card Performance Optimization of Secure Transaction Atomicity Based on Increasing the Class Field Locality. [Citation Graph (, )][DBLP]


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