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Yvon Savaria: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Janusz Rzeszut, Bozena Kaminska, Yvon Savaria
    A new method for testing mixed analog and digital circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:127-132 [Conf]
  2. Olivier Hébert, Ivan C. Kraljic, Yvon Savaria
    A method to derive application-specific embedded processing cores. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:88-92 [Conf]
  3. Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham
    Design For Testability Method for CML Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:360-367 [Conf]
  4. Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid
    The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:698-703 [Conf]
  5. N. Ignat, B. Nicolescu, Yvon Savaria, Gabriela Nicolescu
    Soft-error classification and impact analysis on real-time operating systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:182-187 [Conf]
  6. Abdelaziz Ammari, Régis Leveugle, B. Nicolescu, Yvon Savaria
    Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:488-493 [Conf]
  7. J. Crépeau, Claude Thibeault, Yvon Savaria
    Some Results on Yield and Local Design Rule Relaxation. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:144-151 [Conf]
  8. Daniel Audet, Steve Masson, Yvon Savaria
    Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:241-0 [Conf]
  9. Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault
    Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:157-165 [Conf]
  10. Michel Kafrouni, Claude Thibeault, Yvon Savaria
    A Cost Model for VLSI / MCM Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:148-156 [Conf]
  11. Rachid Kermouche, Yvon Savaria
    Defect and Fault Tolerant Scan Chains. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:185-193 [Conf]
  12. Meng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer
    IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:18-25 [Conf]
  13. B. Nicolescu, P. Peronnard, Raoul Velazco, Yvon Savaria
    Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:377-384 [Conf]
  14. B. Nicolescu, Yvon Savaria, Raoul Velazco
    SIED: Software Implemented Error Detection. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:589-596 [Conf]
  15. Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault
    Yield Modeling of a WSI Telecom Router Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:314-324 [Conf]
  16. Abdessatar Abderrahman, Bozena Kaminska, Yvon Savaria
    Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:658- [Conf]
  17. Cynthia Cousineau, François Laperle, Yvon Savaria
    Design of a JTAG Based Run Time Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:268-269 [Conf]
  18. Pascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria
    A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:304-305 [Conf]
  19. J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier
    A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:50-55 [Conf]
  20. Hung Tien Bui, Yvon Savaria
    High speed differential pulse-width control loop based on frequency-to-voltage converters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:53-56 [Conf]
  21. Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
    Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:221-224 [Conf]
  22. Mohamed Nekili, Yvon Savaria, Guy Bois
    Design of Clock Distribution Networks in Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:95-102 [Conf]
  23. Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria
    Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:546-552 [Conf]
  24. Olivier Duval, L.-P. Lafrance, Yvon Savaria, Pierre Desjardins
    An Integrated Test Platform for Nanostructure Electrical Characterization. [Citation Graph (0, 0)][DBLP]
    ICMENS, 2004, pp:237-242 [Conf]
  25. Mohammed Layachi, Yvon Savaria, Alain Rochefort
    The Effect of p-Coupling on the Electronic Properties of 1, 4-Dithiol Benzene Stacking. [Citation Graph (0, 0)][DBLP]
    ICMENS, 2004, pp:588-592 [Conf]
  26. B. Nicolescu, Yvon Savaria, Raoul Velazco
    Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:233-238 [Conf]
  27. Dorin Emil Calbaza, Ioan Cordos, Nigel Seth-Smith, Yvon Savaria
    An ADPLL circuit using a DDPS for genlock applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:569-572 [Conf]
  28. Hung Tien Bui, Yvon Savaria
    Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:369-372 [Conf]
  29. Jean-Francois Crespo, Pierre Lavoie, Yvon Savaria
    Fast Convergence with Low Precision Weights in ART1 Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:237-240 [Conf]
  30. Dinh Hung Dang, Yvon Savaria, Mohamad Sawan
    A novel approach for implementing ultra-high speed flash ADC using MCML circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6158-6161 [Conf]
  31. Olivier Duval, Yvon Savaria
    An on-chip delay measurements module for nanostructures characterization. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:721-724 [Conf]
  32. Sameh Ghannoum, Dmitri Chtchvyrkov, Yvon Savaria
    A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:347-350 [Conf]
  33. Naim Ben Hamida, Bozena Kaminska, Yvon Savaria
    Initiability: A Measure of Sequential Testability. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1619-1622 [Conf]
  34. Naim Ben Hamida, Bozena Kaminska, Yvon Savaria
    Pseudo-Random Vector Compaction for Sequential Testability. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:63-66 [Conf]
  35. Badre Izouggaghen, Abdelhakim Khouas, Yvon Savaria
    Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:389-392 [Conf]
  36. H. Khali, Jean-Louis Houle, Yvon Savaria
    A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1971-1974 [Conf]
  37. D. Marche, Yves Gagnon, Yvon Savaria
    . A new switch compensation technique for inverted R-2R ladder DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:196-199 [Conf]
  38. Mohamed Nekili, Yvon Savaria
    Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2023-2026 [Conf]
  39. Mohamed Nekili, Yvon Savaria, Guy Bois
    A Fast Low-Power Driver for Long Interconnections in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:343-346 [Conf]
  40. Simon Rioux, Alain Lacourse, Yvon Savaria, Michel Meunier
    Design methods for CMOS low-current finely tunable voltage references covering a wide output range. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4257-4260 [Conf]
  41. Mathieu Renaud, Yvon Savaria
    A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:148-151 [Conf]
  42. Max-Elie Salomon, Abdelhakim Khouas, Yvon Savaria
    A complete spurs distribution model for direct digital period synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4859-4862 [Conf]
  43. Yvon Savaria, Dmitri Chtchvyrkov, John F. Currie
    A Fast CMOS Voltage-Controlled Ring Oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:359-362 [Conf]
  44. Mohamed Soufi, Yvon Savaria, Bozena Kaminska
    On Using Partial Reset for Pseudo-Random Testing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:949-952 [Conf]
  45. Yiyan Tang, Lie Qian, Yuke Wang, Yvon Savaria
    A new memory reference reduction method for FFT implementation on DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:496-499 [Conf]
  46. Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie
    An automatic word length determination method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:53-56 [Conf]
  47. L. Theriault, D. Auder, Yvon Savaria
    Performance estimators for hardware/software co-design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:17-20 [Conf]
  48. Y. Fouzar, Yvon Savaria, Mohamad Sawan
    A new controlled gain phase-locked loop technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:810-813 [Conf]
  49. Mohamed Nekili, Yvon Savaria, Guy Bois
    Minimizing process-induced skew using delay tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:426-429 [Conf]
  50. B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois
    Development of a high performance TSPC library for implementation of large digital building blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:443-446 [Conf]
  51. Dorin Emil Calbaza, Yvon Savaria
    Jitter model of direct digital synthesis clock generators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:1-4 [Conf]
  52. Zhong-Fang Jin, J.-J. Laurin, Yvon Savaria, P. Garon
    A new approach to analyze interconnect delays in RC wire models. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:246-249 [Conf]
  53. Kevin Peterson, Yvon Savaria
    Assertion-based on-line verification and debug environment for complex hardware systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:685-688 [Conf]
  54. A. Bendali, Yvon Savaria
    Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:201-204 [Conf]
  55. Y. Fouzar, Yvon Savaria, Mohamad Sawan
    A CMOS phase-locked loop with an auto-calibrated VCO. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:177-180 [Conf]
  56. L.-P. Lafrance, M.-A. Cantin, Yvon Savaria, S. H. Sung, Pierre Lavoie
    Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:823-826 [Conf]
  57. Mathieu Renaud, Yvon Savaria
    A linear phase detector for arbitrary clock signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:775-778 [Conf]
  58. Wei Ling, Yvon Savaria
    Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:688-693 [Conf]
  59. Noureddine Chabini, Yvon Savaria
    Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:209-214 [Conf]
  60. Bozena Kaminska, Yvon Savaria
    Design-for-Testability Using Test Design Yield and Decision Theory. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:884-892 [Conf]
  61. Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes
    A Design for Machines with Built-In Tolerance to Soft Errors. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:649-659 [Conf]
  62. Yvon Savaria, Bruno Laguë, Bozena Kaminska
    A Pragmatic Approach to the Design of Self-Testing Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:745-754 [Conf]
  63. Hung Tien Bui, Yvon Savaria
    10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:115-118 [Conf]
  64. Hung Tien Bui, Yvon Savaria
    A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:557-562 [Conf]
  65. L.-P. Lafrance, Yvon Savaria
    A Framework for Implementing Reusable Digital Signal Processing Modules. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:51-54 [Conf]
  66. Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid
    Interface-based Design of Systems-on-Chip using UML-RT. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:39-44 [Conf]
  67. Robert Grou-Szabo, Hany Ghattas, Yvon Savaria, Gabriela Nicolescu
    Component-Based Methodology for Hardware Design of a Dataflow Processing Network. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:289-294 [Conf]
  68. D. Morin, F. Normandin, M.-E. Grandmaison, H. Dang, Yvon Savaria, Mohamad Sawan
    An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:111-114 [Conf]
  69. Pascal Nsame, Yvon Savaria
    A Customizable Embedded SoC Platform Architecture. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:299-304 [Conf]
  70. Bill Pontikakis, François R. Boyer, Yvon Savaria
    Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:454-458 [Conf]
  71. S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron
    Automating Functional Coverage Analysis Based on an Executable Specification. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:228-234 [Conf]
  72. S. Regimbal, Yvon Savaria, Guy Bois
    Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:87-92 [Conf]
  73. Ami Castonguay, Yvon Savaria
    A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:264-266 [Conf]
  74. Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst
    Tools for the Characterization of Bipolar CML Testability. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:388-395 [Conf]
  75. Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska
    Design and performance of CMOS TSPC cells for high speed pseudo random testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:368-373 [Conf]
  76. Mohamed Soufi, Yvon Savaria, Bozena Kaminska
    On the design of at-speed testable VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:290-295 [Conf]
  77. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:6-112 [Journal]
  78. Marc-André Cantin, S. Regimbal, S. Catudal, Yvon Savaria
    A Unified Environment to Assess Image Quality in Video Processing. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:6, pp:1289-1306 [Journal]
  79. Eric Granger, Yvon Savaria, Pierre Lavoie
    A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 2003, v:25, n:4, pp:524-528 [Journal]
  80. Daniel Audet, Yvon Savaria, Jean-Louis Houle
    Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1992, v:18, n:2, pp:149-167 [Journal]
  81. Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska
    Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:10, pp:1251-1256 [Journal]
  82. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
    A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:687-698 [Journal]
  83. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
    Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:724-728 [Journal]
  84. Yves Blaquière, Michel Dagenais, Yvon Savaria
    Timing analysis speed-up using a hierarchical and a multimode approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:2, pp:244-255 [Journal]
  85. Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie
    A Metric for Automatic Word-Length Determination of Hardware Datapaths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2228-2231 [Journal]
  86. Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
    Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:346-351 [Journal]
  87. François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer
    Optimal design of synchronous circuits using software pipelining techniques. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:516-532 [Journal]
  88. Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria
    Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:187-204 [Journal]
  89. Syed Rafay Hasan, Yvon Savaria
    Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:629-632 [Conf]
  90. Vincent Binet, Yvon Savaria, Michel Meunier, Yves Gagnon
    Modeling the Substrate Noise Injected by a DC-DC Converter. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:309-312 [Conf]
  91. Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria
    Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:709-712 [Conf]
  92. R. Chebli, Mohamad Sawan, Yvon Savaria, Kamal El-Sankary
    High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3343-3346 [Conf]
  93. Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
    A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:633-636 [Conf]
  94. Ali Naderi, Mohamad Sawan, Yvon Savaria
    A novel 2-GHz band-pass delta modulator dedicated to wireless receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  95. S. Hashemi, Mohamad Sawan, Yvon Savaria
    A power planning model for implantable stimulators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  96. Bill Pontikakis, François R. Boyer, Yvon Savaria
    A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  97. Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria
    Zero skew differential clock distribution network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  98. Ami Castonguay, Yvon Savaria
    Architecture of a hypertransport tunnel. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  99. Z. Huang, Yvon Savaria, Mohamad Sawan, R. Meinga
    High-voltage operational amplifier based on dual floating-gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  100. M. Mbaye, D. Lebel, Normand Bélanger, Yvon Savaria, Samuel Pierre
    Design exploration with an application-specific instruction-set processor for ELA deinterlacing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  101. Ali Naderi, Mohamad Sawan, Yvon Savaria
    Design of an Active-RC Bandpass Filter for a Subsampling RF Delta Modulator. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:967-970 [Conf]
  102. Daniel Audet, Yvon Savaria, N. Arel
    Pipelining communications in large VLSI/ULSI systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:1-10 [Journal]
  103. Mohamed Nekili, Guy Bois, Yvon Savaria
    Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:161-174 [Journal]
  104. B. Bosi, Guy Bois, Yvon Savaria
    Reconfigurable pipelined 2-D convolvers for fast digital signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:299-308 [Journal]
  105. Zhong-Fang Jin, J.-J. Laurin, Yvon Savaria
    A practical approach to model long MIS interconnects in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:494-507 [Journal]
  106. H. Khali, Yvon Savaria, Jean-Louis Houle
    A system level implementation strategy and partitioning heuristic for LUT-based applications. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2005, v:31, n:7, pp:485-502 [Journal]
  107. N. Gorse, P. Bélanger, Alexandre Chureau, El Mostapha Aboulhamid, Yvon Savaria
    A high-level requirements engineering methodology for electronic system-level design. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:4, pp:249-268 [Journal]
  108. Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
    A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:3, pp:297-315 [Journal]

  109. Loop-oriented metrics for exploring an application-specific architecture design-space. [Citation Graph (, )][DBLP]


  110. An interconnect-aware delay model for dynamic voltage scaling in NM technologies. [Citation Graph (, )][DBLP]


  111. Application specific instruction-set processor generation for video processing based on loop optimization. [Citation Graph (, )][DBLP]


  112. Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. [Citation Graph (, )][DBLP]


  113. Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator. [Citation Graph (, )][DBLP]


  114. A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. [Citation Graph (, )][DBLP]


  115. Implementation of a cycle by cycle variable speed processor. [Citation Graph (, )][DBLP]


  116. Parameters estimation applied to automatic video processing algorithms validation. [Citation Graph (, )][DBLP]


  117. Modeling and simulation of complex heterogeneous systems. [Citation Graph (, )][DBLP]


  118. FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders. [Citation Graph (, )][DBLP]


  119. Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. [Citation Graph (, )][DBLP]


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