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Publications of Author

1. Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir
   Testability Improvement During High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2003, pp:505- [Conf]
   
2. Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
   A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. [Citation Graph (0, 0)][DBLP]
   DDECS, 2007, pp:247-250 [Conf]
   
3. Amin Farmahini Farahani, Mehdi Kamal, Seid Mehdi Fakhraie, Saeed Safari
   HW/SW partitioning using discrete particle swarm. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:359-364 [Conf]
   
4. Soheil Aminzadeh, Saeed Safari
   Co-evolutionary high-level test synthesis. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:67-72 [Conf]
   
5. Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir
   A novel improvement technique for high-level test synthesis. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:609-612 [Conf]
   
6. MohammadReza EffatParvar, Karim Faez, Mehdi EffatParvar, Mehdi Zarei, Saeed Safari
   An Intelligent MLFQ Scheduling Algorithm (IMLFQ) with Fault Tolerant Mechanism. [Citation Graph (0, 0)][DBLP]
   ISDA (3), 2006, pp:80-85 [Conf]
   
7. Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilzadeh
   A parameterized graph-based framework for high-level test synthesis. [Citation Graph (0, 0)][DBLP]
   Integration, 2006, v:39, n:4, pp:363-381 [Journal]
   
8. Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari
   Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. [Citation Graph (0, 0)][DBLP]
   AICCSA, 2007, pp:528-534 [Conf]
   
9. 
   Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence. [Citation Graph (, )][DBLP]
   
   
10. 
    Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction. [Citation Graph (, )][DBLP]
    
    
11. 
    On-Chip Verification of NoCs Using Assertion Processors. [Citation Graph (, )][DBLP]
    
    
12. 
    Reliability in Application Specific Mesh-Based NoC Architectures. [Citation Graph (, )][DBLP]
    
    
13. 
    A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. [Citation Graph (, )][DBLP]
    
    
14. 
    Co-evolutionary reliability-oriented high-level synthesis. [Citation Graph (, )][DBLP]
    
    
15. 
    A 65nm 10GHz pipelined MAC structure. [Citation Graph (, )][DBLP]
    
    
16. 
    Real-Time Parallel Implementation of SSD Stereo Vision Algorithm on CSX SIMD Architecture. [Citation Graph (, )][DBLP]
    
    
17. 
    Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips. [Citation Graph (, )][DBLP]
    
    
18. 
    Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips. [Citation Graph (, )][DBLP]
    
    
19. 
    A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages. [Citation Graph (, )][DBLP]