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Jürgen Schlöffel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel
    A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:22-27 [Conf]
  2. Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
    Fault detection and diagnosis with parity trees for space compaction of test responses. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1095-1098 [Conf]
  3. Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
    Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:174-182 [Conf]
  4. Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers
    Synthesis of irregular combinational functions with large don't care sets. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:287-292 [Conf]
  5. Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:212-217 [Conf]
  6. Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel
    PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:306-315 [Conf]
  7. Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
    ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:354-359 [Conf]
  8. Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel
    Implementing a Scheme for External Deterministic Self-Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:101-106 [Conf]
  9. Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
    X-masking during logic BIST and its impact on defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:193-202 [Journal]
  10. Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:181-187 [Conf]
  11. Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
    Deterministic Logic BIST for Transition Fault Testing. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:123-130 [Conf]
  12. Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel
    Computation and Application of Absolute Dominators in Industrial Designs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:137-144 [Conf]

  13. Resistive Bridging Fault Simulation of Industrial Circuits. [Citation Graph (, )][DBLP]


  14. Experimental Studies on SAT-Based ATPG for Gate Delay Faults. [Citation Graph (, )][DBLP]


  15. Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. [Citation Graph (, )][DBLP]


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