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Ming-Der Shieh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu
    High-speed generation of LFSR signatures. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:222-0 [Conf]
  2. Chie Dou, Ming-Der Shieh
    A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:149-0 [Conf]
  3. Chin-Long Wey, Ming-Der Shieh, P. David Fisher
    ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:159-162 [Conf]
  4. Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu
    Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5254-5257 [Conf]
  5. Chien-Ming Wu, Ming-Der Shieh, Hsin-Fu Lo, Min-Hsiung Hu
    Implementation of channel demodulator for DAB system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:137-140 [Conf]
  6. Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh
    A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:446-449 [Conf]
  7. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:33-36 [Conf]
  8. Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu
    Design of an efficient FFT processor for DAB system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:654-657 [Conf]
  9. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
    VLSI architecture of extended in-place path metric update for Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:206-209 [Conf]
  10. Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
    An area-efficient versatile Reed-Solomon decoder for ADSL. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:517-520 [Conf]
  11. Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu
    A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:500-503 [Conf]
  12. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo
    VLSI architecture exploration for sliding-window Log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:513-516 [Conf]
  13. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu
    Memory arrangements in turbo decoders using sliding-window BCJR algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:557-560 [Conf]
  14. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:733-736 [Conf]
  15. Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo
    A Systematic Approach for Parallel CRC Computations. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2001, v:17, n:3, pp:445-461 [Journal]
  16. Chin-Long Wey, Ming-Der Shieh
    Design of a High-Speed Square Generator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:9, pp:1021-1026 [Journal]
  17. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:375-380 [Journal]
  18. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen
    VLSI architectural design tradeoffs for sliding-window log-MAP decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:439-447 [Journal]
  19. Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin
    A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3780-3783 [Conf]
  20. Ming-Der Shieh, Yung-Kuei Lu, Shen-Ming Chung, Jun-Hong Chen
    Design and implementation of efficient Reed-Solomon decoders for multi-mode applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  21. Jing-Shiun Lin, Chung-Kung Lee, Ming-Der Shieh, Jun-Hong Chen
    High-speed CRC design for 10 Gbps applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  22. Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang
    Efficient path metric access for reducing interconnect overhead in Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  23. Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors. [Citation Graph (, )][DBLP]


  24. High-speed modular multiplication design for public-key cryptosystems. [Citation Graph (, )][DBLP]


  25. A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m). [Citation Graph (, )][DBLP]


  26. Modified Subspace Based Channel Estimation Algorithm for OFDM Systems. [Citation Graph (, )][DBLP]


  27. Subspace-Based Blind Channel Estimation for OFDM Systems with Conjugate-Symmetric Property. [Citation Graph (, )][DBLP]


  28. Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation. [Citation Graph (, )][DBLP]


  29. Hardware/Software Codesign of Resource Constrained Real-Time Systems. [Citation Graph (, )][DBLP]


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