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Ming-Hwa Sheu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu
    High-speed generation of LFSR signatures. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:222-0 [Conf]
  2. Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu
    A Fast Additive Normalization Method for Exponential Computation. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:286-293 [Conf]
  3. Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu
    A High Throughput-Rate Architecture for 8*8 2-D DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1578-1590 [Conf]
  4. Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu
    An Expandable Chip Desing for Gray-scale Morphological Operations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1563-1566 [Conf]
  5. Hsien-Huang Wu, Ming-Hwa Sheu, Tung-Yu Yang
    Directional interpolation for field-sequential stereoscopic video. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2879-2882 [Conf]
  6. Shyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu
    VLSI architecture design for a fast parallel label assignment in binary image. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2393-2396 [Conf]
  7. Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh
    A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:446-449 [Conf]
  8. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
    VLSI architecture of extended in-place path metric update for Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:206-209 [Conf]
  9. Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu, Jia-Lin Sheu
    A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:500-503 [Conf]
  10. Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw
    Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. [Citation Graph (0, 0)][DBLP]
    PCM (1), 2005, pp:291-302 [Conf]
  11. Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw, Ming-che Chen
    Film-to-Video Conversion with Scene Cut Detection. [Citation Graph (0, 0)][DBLP]
    ICICIC (1), 2006, pp:285-289 [Conf]
  12. Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen, Hsin-Fu Lo
    A Systematic Approach for Parallel CRC Computations. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2001, v:17, n:3, pp:445-461 [Journal]
  13. Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai
    Fast Fair Crossbar Scheduler for On-chip Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:385-388 [Conf]
  14. Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho
    A high speed and energy efficient full adder design using complementary & level restoring carry logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. Chung-Chi Lin, Chih-Jen Wei, Ming-Hwa Sheu, Huann-Keng Chiang, Chishyan Liaw
    The VLSI design of de-interlacing with scene change detection. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  16. The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing. [Citation Graph (, )][DBLP]

  17. The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection. [Citation Graph (, )][DBLP]

  18. Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. [Citation Graph (, )][DBLP]

  19. Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1). [Citation Graph (, )][DBLP]

  20. Fast design approach for implementing the approximate squaring function. [Citation Graph (, )][DBLP]

  21. Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. [Citation Graph (, )][DBLP]

  22. Low Power Multipliers Using Enhenced Row Bypassing Schemes. [Citation Graph (, )][DBLP]

  23. Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. [Citation Graph (, )][DBLP]

  24. Automatic Generation of Programmable Parallel CRC & Scrambler Designs. [Citation Graph (, )][DBLP]

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