The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Virendra Singh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Software-Based Delay Fault Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:68-71 [Conf]
  2. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Testing Superscalar Processors in Functional Mode. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:747-750 [Conf]
  3. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-based delay fault self-testing of pipelined processor cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5686-5689 [Conf]
  4. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Delay Fault Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:933-0 [Conf]
  5. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Delay Fault Testing of Processor Cores in Functional Mode. [Citation Graph (0, 0)][DBLP]
    IEICE Transactions, 2005, v:88, n:3, pp:610-618 [Journal]
  6. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1203-1215 [Journal]

  7. Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. [Citation Graph (, )][DBLP]


  8. Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. [Citation Graph (, )][DBLP]


  9. Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. [Citation Graph (, )][DBLP]


  10. Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. [Citation Graph (, )][DBLP]


  11. Estimating Error-probability and its Application for Optimizing Roll-back Recovery with Checkpointing. [Citation Graph (, )][DBLP]


  12. Polynomial coefficient based DC testing of non-linear analog circuits. [Citation Graph (, )][DBLP]


  13. DX-compactor: distributed X-compaction for SoCs. [Citation Graph (, )][DBLP]


  14. Energy-efficient redundant execution for chip multiprocessors. [Citation Graph (, )][DBLP]


  15. Graph theoretic approach for scan cell reordering to minimize peak shift power. [Citation Graph (, )][DBLP]


  16. On Minimization of Test Application Time for RAS. [Citation Graph (, )][DBLP]


  17. Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. [Citation Graph (, )][DBLP]


  18. On Minimization of Peak Power for Scan Circuit during Test. [Citation Graph (, )][DBLP]


  19. Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. [Citation Graph (, )][DBLP]


  20. Modified T-Flip-Flop based scan cell for RAS. [Citation Graph (, )][DBLP]


Search in 0.029secs, Finished in 0.030secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002