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Shyh-Jye Jou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting
    Syndrome Simulation And Syndrome Test For Unscanned Interconnects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:62-67 [Conf]
  2. Chauchin Su, Shenshung Chiang, Shyh-Jye Jou
    Impulse response fault model and fault extraction for functional level analog circuit diagnosis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:631-636 [Conf]
  3. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting
    Metrology for analog module testing using analog testability bus. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:594-599 [Conf]
  4. Shyh-Jye Jou, Hui-Hsuan Wang
    Fixed-Width Multiplier for DSP Application. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:318-322 [Conf]
  5. Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su
    A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:574-577 [Conf]
  6. Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu
    A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:293-296 [Conf]
  7. Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su
    Circuits Design Optimization Using Symbolic Approach. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1396-1399 [Conf]
  8. Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang
    A 12.5 Gbps CMOS input sampler for serial link receiver front end. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1055-1058 [Conf]
  9. Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang
    Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:21-24 [Conf]
  10. Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou
    Parameterized and low power DSP core for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:265-268 [Conf]
  11. Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou
    4/2 PAM serial link transmitter with tunable pre-emphasis. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:952-958 [Conf]
  12. Maw-Ching Liu, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou
    Low-power multiplierless FIR filter synthesizer based on CSD code. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:666-669 [Conf]
  13. Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu
    A serial link transceiver for USB2 high-speed mode. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:72-75 [Conf]
  14. Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou
    Sub-word and reduced-width Booth multipliers for DSP applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:575-578 [Conf]
  15. Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao
    An embedded DSP core for wireless communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:524-527 [Conf]
  16. Chauchin Su, Kychin Hwang, Shyh-Jye Jou
    An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:670-676 [Conf]
  17. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
    Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:499-508 [Conf]
  18. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
    Intrinsic response for analog module testing using an analog testability bus. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:2, pp:226-243 [Journal]
  19. Wei-Chang Liu, Ting-Chen Wei, Shyh-Jye Jou
    Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2092-2095 [Conf]
  20. Ting-Zhen Wei, Shyh-Jye Jou, Muh-Tian Shiue
    Memory reduction ICFO estimation architecture for DVB-T. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  21. A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. [Citation Graph (, )][DBLP]


  22. Symbol and carrier frequency offset synchronization for IEEE802.16e. [Citation Graph (, )][DBLP]


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