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Susmita Sur-Kolay: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy
    Fsimac: a fault simulator for asynchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:114-119 [Conf]
  2. Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta
    Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. [Citation Graph (0, 0)][DBLP]
    ICIT, 2006, pp:281-284 [Conf]
  3. Susmita Sur-Kolay, Bhargab B. Bhattacharya
    Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:69-74 [Conf]
  4. Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang
    A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1078-1083 [Conf]
  5. Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy
    Fast FPGA Placement using Space-filling Curve. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:415-420 [Conf]
  6. Abhik Roychoudhury, Susmita Sur-Kolay
    Efficient Algorithms for Vertex Arboricity of Planar Graphs. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1995, pp:37-51 [Conf]
  7. Susmita Sur-Kolay, Bhargab B. Bhattacharya
    Inherent Nonslicibility of Rectangular Duals in VLSI Floorplanning. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1988, pp:88-107 [Conf]
  8. Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    A unified approach to topology generation and area optimization of general floorplans. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:712-715 [Conf]
  9. Susmita Sur-Kolay, Bhargab B. Bhattacharya
    The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:524-527 [Conf]
  10. Susmita Sur-Kolay, Satyajit Banerjee, C. A. Murthy
    Flavours of Traveling Salesman Problem in VLSI Design. [Citation Graph (0, 0)][DBLP]
    IICAI, 2003, pp:656-667 [Conf]
  11. Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy
    Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:395-398 [Conf]
  12. Parthasarathi Dasgupta, Susmita Sur-Kolay
    Slicibility of rectangular graphs and floorplan optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:150-155 [Conf]
  13. Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
    Combined instruction and loop parallelism in array synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:165-170 [Conf]
  14. Sanjay Goswami, Susmita Sur-Kolay
    Virtual Molecular Computing - Emulating DNA Molecules. [Citation Graph (0, 0)][DBLP]
    IWDC, 2004, pp:95-101 [Conf]
  15. Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
    Optimal Partitioning for FPGA Based Regular Array Implementations. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2000, pp:155-159 [Conf]
  16. Susmita Sur-Kolay, Satyajit Banerjee, S. Mukhopadhyaya, C. A. Murthy
    Genetic Algorithm for Double Digest Problem. [Citation Graph (0, 0)][DBLP]
    PReMI, 2005, pp:623-629 [Conf]
  17. Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    Topological Routing Amidst Polygonal Obstacles. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:274-279 [Conf]
  18. P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    VLSI floorplan generation and area optimization using AND-OR graph search. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:370-375 [Conf]
  19. Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:65-0 [Conf]
  20. Subhashis Majumder, Susmita Sur-Kolay, Subhas C. Nandy, Bhargab B. Bhattacharya, B. Chakraborty
    Hot Spots and Zones in a Chip: A Geometrician's View. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:691-696 [Conf]
  21. Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu
    Test Pattern Generation for Power Supply Droop Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:343-348 [Conf]
  22. Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta
    Partitioning Routing Area into Zones with Distinct Pins. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:345-0 [Conf]
  23. Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah
    Physical Design Trends and Layout-Based Fault Modeling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:6-8 [Conf]
  24. Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
    Floorplanning in Modern FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:893-898 [Conf]
  25. Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma
    A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:111-116 [Conf]
  26. Pritha Banerjee, Susmita Sur-Kolay
    Faster Placer for Island-Style FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:117-121 [Conf]
  27. Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    A unified approach to topology generation and optimal sizing of floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:126-135 [Journal]
  28. Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya
    Manhattan-diagonal routing in channels and switchboxes. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:1, pp:75-104 [Journal]
  29. Parthasarathi Dasgupta, Susmita Sur-Kolay
    Slicible rectangular graphs and their optimal floorplans. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:4, pp:447-470 [Journal]
  30. Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das
    Hierarchical partitioning of VLSI floorplans by staircases. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]

  31. Fast Robust Intellectual Property Protection for VLSI Physical Design. [Citation Graph (, )][DBLP]


  32. Floorplanning for Partial Reconfiguration in FPGAs. [Citation Graph (, )][DBLP]


  33. Encoding of Floorplans through Deterministic Perturbation. [Citation Graph (, )][DBLP]


  34. A Unified Approach for IP Protection across Design Phases in a Packaged Chip. [Citation Graph (, )][DBLP]


  35. MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. [Citation Graph (, )][DBLP]


  36. Nearest Neighbour based Synthesis of Quantum Boolean Circuits. [Citation Graph (, )][DBLP]


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