|
Search the dblp DataBase
Suriyaprakash Natarajan:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. [Citation Graph (0, 0)][DBLP] Asian Test Symposium, 2005, pp:194-201 [Conf]
- Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta
Process Variations and their Impact on Circuit Operation. [Citation Graph (0, 0)][DBLP] DFT, 1998, pp:73-0 [Conf]
- Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
Selecting High-Quality Delay Tests for Manufacturing Test and Debug. [Citation Graph (0, 0)][DBLP] DFT, 2006, pp:59-70 [Conf]
- Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
Switch-level delay test of domino logic circuits. [Citation Graph (0, 0)][DBLP] ITC, 2001, pp:367-376 [Conf]
- Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
Switch-level delay test. [Citation Graph (0, 0)][DBLP] ITC, 1999, pp:171-180 [Conf]
- Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
XIDEN: Crosstalk Target Identification Framework. [Citation Graph (0, 0)][DBLP] ITC, 2002, pp:365-374 [Conf]
- Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty
Path Delay Fault Simulation on Large Industrial Designs. [Citation Graph (0, 0)][DBLP] VTS, 2006, pp:16-23 [Conf]
On efficient generation of instruction sequences to test for delay defects in a processor. [Citation Graph (, )][DBLP]
Case Study on Speed Failure Causes in a Microprocessor. [Citation Graph (, )][DBLP]
Search in 0.001secs, Finished in 0.002secs
|