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Nisar Ahmed: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed
    Low Transition LFSR for BIST-Based Applications. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:138-143 [Conf]
  2. Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
    Timing-based delay test for screening small delay defects. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:320-325 [Conf]
  3. Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani
    Extending JTAG for Testing Signal Integrity in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10218-10223 [Conf]
  4. Nisar Ahmed, Mohammad Tehranipoor
    Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:187-198 [Conf]
  5. Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
    A novel framework for faster-than-at-speed delay test considering IR-drop effects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:198-203 [Conf]
  6. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:554-0 [Conf]
  7. Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani
    Frequency driven repeater insertion for deep submicron. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:181-184 [Conf]
  8. Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani
    Low power pattern generation for BIST architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:689-692 [Conf]
  9. Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
    At-Speed Transition Fault Testing With Low Speed Scan Enable. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:42-47 [Conf]
  10. Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
    Pattern Generation and Estimation for Power Supply Noise Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:439-444 [Conf]
  11. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Testing SoC Interconnects for Signal Integrity Using Boundary Scan. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:158-172 [Conf]
  12. Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
    Supply Voltage Noise Aware ATPG for Transition Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:179-186 [Conf]
  13. Nisar Ahmed, Mohammad Tehranipoor
    Improving Transition Delay Test Using a Hybrid Method. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:402-412 [Journal]
  14. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Testing SoC interconnects for signal integrity using extended JTAG architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:800-811 [Journal]
  15. Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
    Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:533-538 [Conf]

  16. Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. [Citation Graph (, )][DBLP]


  17. Variational Bayesian data fusion of multi-class discrete observations with applications to cooperative human-robot estimation. [Citation Graph (, )][DBLP]


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