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Bin-Da Liu :
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Hsin-Wen Ting , Bin-Da Liu , Soon-Jyh Chang A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 2004, pp:52-57 [Conf ] Pao-Chuan Chen , Bin-Da Liu , Jhing-Fa Wang Overall consideration of scan design and test generation. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:9-12 [Conf ] Lih-Yang Wang , Yen-Tai Lai , Bin-Da Liu , Ting-Chung Chang A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:703-708 [Conf ] Che-Hong Chen , Bin-Da Liu , Jar-Ferr Yang Direct recursive structures for computing radix-r two-dimensional DCT. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2003, pp:269-272 [Conf ] Che-Hong Chen , Bin-Da Liu , Jar-Ferr Yang Condensed recursive structures for computing multi-dimensional DCT with arbitrary length. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2004, pp:405-408 [Conf ] Zhan-Yuan Cheng , Che-Hong Chen , Bin-Da Liu , Jar-Ferr Yang Unified selectable fixed-coefficient recursive structures for computing DCT, IMDCT and subband synthesis filtering. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2004, pp:557-560 [Conf ] Jar-Shone Ker , Yau-Hwang Kuo , Bin-Da Liu Functional Text Pattern Generation for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1519-1522 [Conf ] Bin-Da Liu , Chun-Yueh Huang Array Based Fuzzy Inference Mechanism Implemented with Current-Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:537-540 [Conf ] Heng-Yao Lin , Yi-Chih Chao , Che-Hong Chen , Bin-Da Liu , Jar-Ferr Yang Combined 2-D transform and quantization architectures for H.264 video coders. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2005, pp:1802-1805 [Conf ] Chi-Sheng Lin , Kuan-Hua Chen , Bin-Da Liu Low-power and low-voltage fully parallel content-addressable memory. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:373-376 [Conf ] Hsin-Hung Ou , Bin-Da Liu A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2005, pp:1972-1975 [Conf ] Jing-Jou Tang , Bin-Da Liu , Kuen-Jong Lee An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:393-396 [Conf ] Lih-Yang Wang , Yen-Tai Lai , Bin-Da Liu , Tin-Chung Chang Layout Compaction with Minimzed Delay Bound on Timing Critical Paths. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1849-1852 [Conf ] Chien-Cheng Yu , Wei-Ping Wang , Bin-Da Liu A new level converter for low-power applications. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 2001, pp:113-116 [Conf ] Chung-Bin Wu , Bin-Da Liu , Jar-Ferr Yang Adaptive postprocessors with DCT-based block classifications. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2001, pp:271-274 [Conf ] Chun-Yueh Huang , Gwo-Jeng Yu , Bin-Da Liu A hardware design approach for merge-sorting network. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2001, pp:534-537 [Conf ] Shin-Hong Ou , Chi-Sheng Lin , Bin-Da Liu A scalable sorting architecture based on maskable WTA/MAX circuit. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2002, pp:209-212 [Conf ] Chi-Sheng Lin , Bin-Da Liu Design of a pipelined and expandable sorting architecture with simple control scheme. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2002, pp:217-220 [Conf ] Hui-Chin Tseng , Hsin-Hung Ou , Chi-Sheng Lin , Bin-Da Liu A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. [Citation Graph (0, 0)][DBLP ] ISLPED, 2004, pp:252-256 [Conf ] Jianwei Zhang , Yizheng Ye , Binda Liu A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. [Citation Graph (0, 0)][DBLP ] ISLPED, 2006, pp:135-138 [Conf ] Lih-Yang Wang , Yen-Tai Lai , Bin-Da Liu , Tin-Chung Chang Performance-directed compaction for VLSI symbolic layouts. [Citation Graph (0, 0)][DBLP ] Computer-Aided Design, 1995, v:27, n:1, pp:65-74 [Journal ] Wen-Bin Lin , Bin-Da Liu Coefficients Generation for the 4th-Order Leapfrog Sigma-Delta A/D Converters. [Citation Graph (0, 0)][DBLP ] IEICE Transactions, 2004, v:87, n:1, pp:231-242 [Journal ] Jing-Jou Tang , Kuen-Jong Lee , Bin-Da Liu A graph representation for programmable logic arrays to facilitate testing and logic design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1030-1043 [Journal ] Chung-Bin Wu , Bin-Da Liu , Jar-Ferr Yang Adaptive postprocessors with DCT-based block classifications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:5, pp:365-375 [Journal ] Chung-Bin Wu , C.-Y. Yao , Bin-Da Liu , Jar-Ferr Yang DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:5, pp:694-703 [Journal ] Bin-Da Liu , Chuen-Yau Chen , Ju-Ying Tsao Design of adaptive fuzzy logic controller based on linguistic-hedge concepts and genetic algorithms. [Citation Graph (0, 0)][DBLP ] IEEE Transactions on Systems, Man, and Cybernetics, Part B, 2001, v:31, n:1, pp:32-53 [Journal ] Bin-Da Liu , Chun-Yueh Huang Design and implementation of the tree-based fuzzy logic controller. [Citation Graph (0, 0)][DBLP ] IEEE Transactions on Systems, Man, and Cybernetics, Part B, 1997, v:27, n:3, pp:475-487 [Journal ] Yi-Chih Chao , Shih-Tse Wei , Jar-Ferr Yang , Bin-Da Liu Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:3135-3138 [Conf ] Li-Chuan Chang , Yen-Sung Chen , Rung-Wen Liou , Chih-Hung Kuo , Chia-Hung Yeh , Bin-Da Liu A Real Time and Low Cost Hardware Architecture for Video Abstraction System. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:773-776 [Conf ] Heng-Yao Lin , Ying-Hong Lu , Bin-Da Liu , Jar-Ferr Yang Low power design of H.264 CAVLC decoder. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Heng-Yao Lin , Jwu-Jin Yang , Bin-Da Liu , Jar-Ferr Yang Efficient deblocking filter architecture for H.264 video coders. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Jing-Jou Tang , Kuen-Jong Lee , Bin-Da Liu A practical current sensing technique for IDDQ testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:302-310 [Journal ] Lossless image and video coding based on H.264/AVC intra predictions with simplified interpolations. [Citation Graph (, )][DBLP ] A Novel Design for Computation of All Transforms in H.264/AVC Decoders. [Citation Graph (, )][DBLP ] An approximate square criterion for H.264/AVC intra mode decision. [Citation Graph (, )][DBLP ] System level design of a spatio-temporal video resampling architecture. [Citation Graph (, )][DBLP ] Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding. [Citation Graph (, )][DBLP ] A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. [Citation Graph (, )][DBLP ] A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter. [Citation Graph (, )][DBLP ] A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories. [Citation Graph (, )][DBLP ] An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. [Citation Graph (, )][DBLP ] The high-resolution multi-tone signal generators. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.306secs