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Publications of Author

1. Shing-Wu Tung, Jing-Yang Jou
   Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1998, pp:402-407 [Conf]
   
2. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
   An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2001, pp:431-436 [Conf]
   
3. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
   SoC design integration by using automatic interconnection rectification. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2003, pp:744-747 [Conf]
   
4. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
   An AVPG for SOC design verification with port order fault model. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2001, pp:259-262 [Conf]
   
5. Chih-Yuan Chen, Shing-Wu Tung
   ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:405-408 [Conf]
   
6. Shing-Wu Tung, Jing-Yang Jou
   A Logical Fault Model for Library Coherence Checking. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 1998, v:14, n:3, pp:567-586 [Journal]
   
7. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
   On automatic-verification pattern generation for SoC withport-order fault model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:466-479 [Journal]
   
8. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
   An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1225-1232 [Journal]
   
9. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
   Automatic interconnection rectification for SoC design verification based on the port order fault model. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:104-114 [Journal]