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Fabian Vargas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Fabian Vargas, Alexandre M. Amory
    Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:417-422 [Conf]
  2. Fabian Vargas, E. Bezerra, L. Wulff, Daniel Barros Jr.
    Optimizing HW/SW Codesign towards Reliability for Critical-Application Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:52-57 [Conf]
  3. Fabian Vargas, Rubem Dutra R. Fagundes, Daniel Barros Jr.
    Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:224-229 [Conf]
  4. Fabian Vargas, Rubem Dutra R. Fagundes, Daniel Barros Jr., Diogo B. Brum
    Briefing a New Approach to Improve the EMI Immunity of DSP Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:468-473 [Conf]
  5. Fabian Vargas, Djones Lettnin, Diogo B. Brum, Dárcio Prestes
    A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:218-223 [Conf]
  6. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:295-300 [Conf]
  7. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:50-58 [Conf]
  8. Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Modeling and Simulation of Time Domain Faults in Digital Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:5-10 [Conf]
  9. Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    Hybrid Soft Error Detection by Means of Infrastructure IP Cores. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:79-88 [Conf]
  10. Fabian Vargas, D. L. Cavalcante, E. Gatti, Dárcio Prestes, D. Lupi
    On the Proposition of an EMI-Based Fault Injection Approach. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:207-208 [Conf]
  11. Fabian Vargas, Alexandre M. Amory, Raoul Velazco
    Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:67-72 [Conf]
  12. Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Leticia Maria Veiras Bolzani, E. Rhod, Matteo Sonza Reorda
    Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:163- [Conf]
  13. Fabian Vargas, Rubem Dutra R. Fagundes, Daniel Barros Jr.
    A New Approach to Design Reliable Real-Time Speech Recognition Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:187-191 [Conf]
  14. Fabian Vargas, Rubem Dutra R. Fagundes, Daniel Barros Jr.
    A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:187- [Conf]
  15. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:257-262 [Conf]
  16. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:281-286 [Conf]
  17. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:207-212 [Conf]
  18. Fabian Vargas, Michael Nicolaidis, Yervant Zorian
    An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:345-354 [Conf]
  19. Fabian Vargas, Maria Cristina Felippetto de Castro, Marcello Macarthy, Djones Lettnin
    Electrocardiogram Pattern Recognition by Means of MLP Network and PCA: A Case Study on Equal Amount of Input Signal Types. [Citation Graph (0, 0)][DBLP]
    SBRN, 2002, pp:200-205 [Conf]
  20. Fabian Vargas
    2006 Latin American Test Workshop. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:185- [Journal]
  21. Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    A New Hybrid Fault Detection Technique for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:2, pp:185-198 [Journal]
  22. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:167-172 [Conf]
  23. Fabian Vargas, Leonardo Piccoli, Juliano Benfica, Antonio A. de Alecrim Jr., Marlon Moraes
    Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:93-100 [Conf]
  24. D. Barros Júnior, M. Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, J. P. Teixeira
    Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:349-363 [Journal]

  25. Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. [Citation Graph (, )][DBLP]


  26. Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. [Citation Graph (, )][DBLP]


  27. A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems. [Citation Graph (, )][DBLP]


  28. Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. [Citation Graph (, )][DBLP]


  29. Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. [Citation Graph (, )][DBLP]


  30. Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. [Citation Graph (, )][DBLP]


  31. Briefing power/reliability optimization in embedded software design. [Citation Graph (, )][DBLP]


  32. Design and test on chip for EMC. [Citation Graph (, )][DBLP]


  33. Signal Integrity Enhancement in Digital Circuits. [Citation Graph (, )][DBLP]


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