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Alexandre M. Amory: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Fabian Vargas, Alexandre M. Amory
    Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:417-422 [Conf]
  2. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:62-63 [Conf]
  3. Fabian Vargas, Alexandre M. Amory, Raoul Velazco
    Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:67-72 [Conf]
  4. Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes
    Reducing test time with processor reuse in network-on-chip based systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:111-116 [Conf]
  5. Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes
    Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:174-179 [Conf]
  6. Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes
    DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:435-440 [Conf]
  7. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
    Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:213-218 [Conf]
  8. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

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