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James Patrick Parkerson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
    A Novel Approach for On-line Testable Reversible Logic Circuit Desig. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:325-330 [Conf]
  2. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
    Online Testable Reversible Logic Circuit Design using NAND Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:324-331 [Conf]
  3. C. K. Tang, Parag K. Lala, James Patrick Parkerson
    A Technique for Designing Totally Self-Checking Domino Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:128-132 [Conf]
  4. D. P. Vasudevan, Parag K. Lala, James Patrick Parkerson
    CMOS Realization of Online Testable Reversible Logic Gates. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:309-310 [Conf]
  5. D. P. Vasudevan, James Patrick Parkerson, Parag K. Lala
    Logic implementation using a reversible gate. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2004, pp:452-456 [Conf]

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