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Hsin-Po Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hsin-Po Wang, Jon Turino
    DFT and BIST techniques for the future. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:6-7 [Conf]
  2. Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
    A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:103-0 [Conf]
  3. Xiaoqing Wen, Hsin-Po Wang
    A Flexible Logic BIST Scheme and Its Application to SoC Designs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:463- [Conf]

  4. Type-matching clock tree for zero skew clock gating. [Citation Graph (, )][DBLP]


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