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José Luis Huertas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chin-Long Wey, Adam Osseiran, José Luis Huertas, Yeon-Chen Nieu
    Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:15-0 [Conf]
  2. Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas
    SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:281-286 [Conf]
  3. Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas
    Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:810-814 [Conf]
  4. Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
    Statistical behavioral modeling and characterization of A/D converters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:562-566 [Conf]
  5. Marcelo Lubaszewski, José Luis Huertas
    Test and Design-for-Test of Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IFIP Congress Tutorials, 2004, pp:183-212 [Conf]
  6. Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro
    A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2019-2022 [Conf]
  7. Servando Espejo-Meana, Ángel Rodríguez-Vázquez, Rafael Domínguez-Castro, Bernabé Linares-Barranco, José Luis Huertas
    A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:970-973 [Conf]
  8. Bernabé Linares-Barranco, S. Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José Luis Huertas
    CMOS Continuous BAM With On Chip Learning. [Citation Graph (0, 0)][DBLP]
    IWANN, 1991, pp:322-327 [Conf]
  9. Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, José Luis Huertas
    A Real Time Clustering CMOS Neural Engine. [Citation Graph (0, 0)][DBLP]
    NIPS, 1994, pp:755-762 [Conf]
  10. José Luis Huertas
    Test and design-for-test of mixed-signal integrated circuits. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:4- [Conf]
  11. Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
    Practical Oscillation-Based Test of Integrated Filters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:64-72 [Journal]
  12. Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
    Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:73-82 [Journal]
  13. Adoración Rueda, Michel Renovell, José Luis Huertas
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:203- [Journal]
  14. Diego Vázquez, Gloria Huertas, África Luque, Manuel J. Barragan Asian, Gildas Leger, Adoración Rueda, José Luis Huertas
    Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:221-232 [Journal]

  15. A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis. [Citation Graph (, )][DBLP]


  16. A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. [Citation Graph (, )][DBLP]


  17. Oscillation-Based Test in Data Converters: On-Line Monitoring. [Citation Graph (, )][DBLP]


  18. (Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems. [Citation Graph (, )][DBLP]


  19. A new method for the state reduction of incompletely specified finite sequential machines. [Citation Graph (, )][DBLP]


  20. Total ionizing dose effects in switched-capacitor filters using oscillation-based test. [Citation Graph (, )][DBLP]


  21. A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. [Citation Graph (, )][DBLP]


  22. Low-cost signature test of RF blocks based on envelope response analysis. [Citation Graph (, )][DBLP]


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