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Publications of Author

1. Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa
   On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1998, pp:222-227 [Conf]
   
2. Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki
   Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1999, pp:269-274 [Conf]
   
3. Teruhiko Yamada, Tsuyoshi Sasaki
   On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1996, pp:189-0 [Conf]
   
4. Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey
   A simple technique for locating gate-level faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1995, pp:65-70 [Conf]
   
5. Koji Yamazaki, Teruhiko Yamada
   An approach to diagnose logical faults in partially observable sequential circuits. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 1997, pp:168-173 [Conf]
   
6. Yoshiyuki Koseki, Teruhiko Yamada
   PLAYER: a PLA design system for VLSI's. [Citation Graph (0, 0)][DBLP]
   DAC, 1985, pp:766-769 [Conf]
   
7. Teruhiko Yamada
   Syndrome-Testable Design of Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
   ITC, 1983, pp:453-459 [Conf]
   
8. Teruhiko Yamada
   Accelerating the Pace of R&D in Asia. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1995, v:12, n:3, pp:12-13 [Journal]
   
9. Teruhiko Yamada
   1997 Asian Test Symposium. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:6-0 [Journal]
   
10. Teruhiko Yamada, Takashi Nanya
    Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:8, pp:758-761 [Journal]
    
11. Teruhiko Yamada, Takashi Nanya
    Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:5, pp:511-512 [Journal]