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Edward J. McCluskey: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey
    A simple technique for locating gate-level faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:65-70 [Conf]
  2. Joseph L. A. Hughes, Samiha Mourad, Edward J. McCluskey
    An Experimental Study Comparing 74LS181 Test Sets. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1985, pp:384-387 [Conf]
  3. Edward J. McCluskey
    Hardware Fault-Tolerance. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1985, pp:260-263 [Conf]
  4. Samiha Mourad, Joseph L. A. Hughes, Edward J. McCluskey
    Multiple Fault Detection in Parity Trees. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:441-444 [Conf]
  5. Ahmad A. Al-Yamani, Edward J. McCluskey
    Seed encoding with LFSRs and cellular automata. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:560-565 [Conf]
  6. Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
    Testing Digital Circuits with Constraints. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:195-206 [Conf]
  7. Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey
    Performance Evaluation of Checksum-Based ABFT. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:461-0 [Conf]
  8. Nahmsuk Oh, Edward J. McCluskey
    Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:182-0 [Conf]
  9. Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey
    Fast Run-Time Fault Location in Dependable FPGA-Based Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:206-214 [Conf]
  10. Shu-Yi Yu, Edward J. McCluskey
    Permanent Fault Repair for FPGAs with Limited Redundant Area. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:125-133 [Conf]
  11. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    Techniques for Estimation of Design Diversity for Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DSN, 2001, pp:25-36 [Conf]
  12. Subhasish Mitra, Edward J. McCluskey
    Dependable Reconfigurable Computing Design Diversity and Self Repair. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:5- [Conf]
  13. Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey
    A Reliable LZ Data Compressor on Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:249-258 [Conf]
  14. Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey
    An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:175-184 [Conf]
  15. Samiha Mourad, Joseph L. A. Hughes, Edward J. McCluskey
    Stuck-At Fault Detection in Parity Trees. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:836-840 [Conf]
  16. Edward J. McCluskey
    Reduction of feedback loops in sequential circuits and carry leads in iterative networks [Citation Graph (0, 0)][DBLP]
    FOCS, 1962, pp:91-102 [Conf]
  17. Edward J. McCluskey
    Minimal sums for Boolean functions having many unspecified fundamental products [Citation Graph (0, 0)][DBLP]
    FOCS, 1961, pp:10-17 [Conf]
  18. Edward J. McCluskey
    Logical design theory of NOR gate networks with no complemented inputs [Citation Graph (0, 0)][DBLP]
    FOCS, 1963, pp:137-148 [Conf]
  19. J. F. Poage, Edward J. McCluskey
    Derivation of optimum test sequences for sequential machines [Citation Graph (0, 0)][DBLP]
    FOCS, 1964, pp:121-132 [Conf]
  20. Wei-Je Huang, Edward J. McCluskey
    A memory coherence technique for online transient error recovery of FPGA configurations. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:183-192 [Conf]
  21. Steven D. Millman, Edward J. McCluskey
    Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:154-161 [Conf]
  22. Nirmal R. Saxena, Piero Franco, Edward J. McCluskey
    Bounds on Signature Analysis Aliasing for Random Testing. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:104-113 [Conf]
  23. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    An output encoding problem and a solution technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:304-307 [Conf]
  24. Nur A. Touba, Edward J. McCluskey
    Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:651-654 [Conf]
  25. Nur A. Touba, Edward J. McCluskey
    Pseudo-Random Pattern Testing of Bridging Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:54-60 [Conf]
  26. Hassanein H. Amer, Edward J. McCluskey
    Modeling the Effect of Chip Failures on Cache Memory Systems. [Citation Graph (0, 1)][DBLP]
    ICDE, 1987, pp:340-346 [Conf]
  27. Edward J. McCluskey
    Fundamental Mode and Pulse Mode Operations of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1962, pp:725-730 [Conf]
  28. John F. Wakerly, Edward J. McCluskey
    Design of Low-Cost General-Purpose Self-Diagnosing Computers. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1974, pp:108-111 [Conf]
  29. Ahmad A. Al-Yamani, Edward J. McCluskey
    BIST-Guided ATPG. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:244-249 [Conf]
  30. Subhasish Mitra, Edward J. McCluskey
    Diversity Techniques for Concurrent Error Detection. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:249-250 [Conf]
  31. LaNae J. Avra, Edward J. McCluskey
    Synthesizing for Scan Dependence in Built-In Self-Testable Desings. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:734-743 [Conf]
  32. Saied Bozorgui-Nesbat, Edward J. McCluskey
    Lower Overhead Design for Testability of Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:856-865 [Conf]
  33. Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra
    Speed Clustering of Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1128-1137 [Conf]
  34. Jonathan T.-Y. Chang, Edward J. McCluskey
    Detecting Delay Flaws by Very-Low-Voltage Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:367-376 [Conf]
  35. Jonathan T.-Y. Chang, Edward J. McCluskey
    Detecting resistive shorts for CMOS domino circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:890-899 [Conf]
  36. Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey
    Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:184-193 [Conf]
  37. Cary K. Chin, Edward J. McCluskey
    Test Length for Pseudo Random Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:94-99 [Conf]
  38. Mario L. Côrtes, Edward J. McCluskey
    An Experiment on Intermittent-Failure Mechanisms. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:435-442 [Conf]
  39. Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey
    An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:653-662 [Conf]
  40. Piero Franco, Edward J. McCluskey
    Delay Testing of Digital Circuits by Output Waveform Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:798-807 [Conf]
  41. Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell
    Analysis and Detection of Timing Failures in an Experimental Test Chip. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:691-700 [Conf]
  42. Gregory Freeman, Dick L. Liu, Bruce A. Wooley, Edward J. McCluskey
    Two CMOS Metastability Sensors. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:140-144 [Conf]
  43. Kiyoshi Furuya, Edward J. McCluskey
    Two-Pattern Test Capabilities of Autonomous TPG Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:704-711 [Conf]
  44. Hong Hao, Edward J. McCluskey
    "Resistive Shorts" Within CMOS Gates. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:292-301 [Conf]
  45. Hong Hao, Edward J. McCluskey
    Very-Low-Voltage Testing for Weak CMOS Logic ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:275-284 [Conf]
  46. Syed Zahoor Hassan, Edward J. McCluskey
    Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:320-326 [Conf]
  47. Joseph L. A. Hughes, Edward J. McCluskey
    An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:52-58 [Conf]
  48. Joseph L. A. Hughes, Edward J. McCluskey
    Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:368-374 [Conf]
  49. Chien-Mo James Li, Edward J. McCluskey
    Testing for tunneling opens. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:85-94 [Conf]
  50. Siyad C. Ma, Piero Franco, Edward J. McCluskey
    An Experimental Chip to Evaluate Test Techniques: Experiment Results. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:663-672 [Conf]
  51. Siyad C. Ma, Edward J. McCluskey
    Non-Conventional Faults in BiCMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:882-891 [Conf]
  52. Aamer Mahmood, Edward J. McCluskey, Aydin Ersoz
    Concurrent System-Level Error Detection Using a Watchdog Processor. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:145-152 [Conf]
  53. Aamer Mahmood, Edward J. McCluskey, David J. Lu
    Concurrent Fault Detection Using a Watchdog Processor and Assertions. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:622-628 [Conf]
  54. Samy Makar, Edward J. McCluskey
    On the Testing of Multiplexers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:669-679 [Conf]
  55. Samy Makar, Edward J. McCluskey
    Functional Tests for Scan Chain Latches. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:606-615 [Conf]
  56. Edward J. McCluskey
    Built-In Verification Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1982, pp:183-190 [Conf]
  57. Edward J. McCluskey
    Teaching Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:166-169 [Conf]
  58. Edward J. McCluskey
    Test Teaching. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:235- [Conf]
  59. Edward J. McCluskey
    Practice and Theory. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:203-204 [Conf]
  60. Edward J. McCluskey
    Quality and Single-Stuck Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:597- [Conf]
  61. Edward J. McCluskey, Fred Buelow
    IC Quality and Test Transparency. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:295-301 [Conf]
  62. Edward J. McCluskey, David J. Lu
    Recurrent Test Patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:76-82 [Conf]
  63. Edward J. McCluskey, Chao-Wen Tseng
    Stuck-fault tests vs. actual defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:336-343 [Conf]
  64. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    A design diversity metric and reliability analysis for redundant systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:662-671 [Conf]
  65. Steven D. Millman, Edward J. McCluskey
    Detecting Bridging Faults with Stuck-at Test Sets. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:773-783 [Conf]
  66. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    Scan Synthesis for One-Hot Signals. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:714-722 [Conf]
  67. Subhasish Mitra, Edward J. McCluskey
    Combinational logic synthesis for diversity in duplex systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:179-188 [Conf]
  68. Subhasish Mitra, Edward J. McCluskey
    Which concurrent error detection scheme to choose ? [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:985-994 [Conf]
  69. Samiha Mourad, Edward J. McCluskey
    On Benchmarking Digital Testing Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:997- [Conf]
  70. Robert B. Norwood, Edward J. McCluskey
    Orthogonal Scan: Low-Overhead Scan for Data Paths. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:659-668 [Conf]
  71. Nirmal R. Saxena, Piero Franco, Edward J. McCluskey
    Refined Bounds on Signature Analysis Aliasing for Random Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:818-827 [Conf]
  72. Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey
    Fault Grading FPGA Interconnect Test Configurations. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:608-617 [Conf]
  73. Nur A. Touba, Edward J. McCluskey
    Automated Logic Synthesis of Random-Pattern-Testable Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:174-183 [Conf]
  74. Nur A. Touba, Edward J. McCluskey
    Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:674-682 [Conf]
  75. Nur A. Touba, Edward J. McCluskey
    Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:167-175 [Conf]
  76. Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey
    Testing for resistive opens and stuck opens. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1049-1058 [Conf]
  77. Chao-Wen Tseng, Edward J. McCluskey
    Multiple-output propagation transition fault test. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:358-366 [Conf]
  78. Jon G. Udeli Jr., Edward J. McCluskey
    Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:1000- [Conf]
  79. Laung-Terng Wang, Edward J. McCluskey
    Circuits for Pseudo-Exhaustive Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:25-37 [Conf]
  80. Laung-Terng Wang, Edward J. McCluskey
    A Hybrid Design of Maximum-Length Sequence Generators. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:38-47 [Conf]
  81. Shu-Yi Yu, Edward J. McCluskey
    On-line testing and recovery in TMR systems for real-time applications. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:240-249 [Conf]
  82. Chaohuang Zeng, Nirmal R. Saxena, Edward J. McCluskey
    Finite state machine synthesis with concurrent error detection. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:672-679 [Conf]
  83. Wei-Je Huang, Edward J. McCluskey
    Transient errors and rollback recovery in LZ compression. [Citation Graph (0, 0)][DBLP]
    PRDC, 2000, pp:128-138 [Conf]
  84. David J. Lu, Edward J. McCluskey, Masood Namjoo
    Summary of Structural integrity Checking. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1980, pp:107-109 [Conf]
  85. Ahmad A. Al-Yamani, Edward J. McCluskey
    Built-In Reseeding for Serial Bist. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:63-68 [Conf]
  86. Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
    Bist Reseeding with very few Seeds. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:69-76 [Conf]
  87. Chien-Mo James Li, Edward J. McCluskey
    Diagnosis of Tunneling Opens. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:22-27 [Conf]
  88. Chien-Mo James Li, Edward J. McCluskey
    Diagnosis of Sequence-Dependent Chips. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:187-192 [Conf]
  89. Jonathan T.-Y. Chang, Edward J. McCluskey
    Quantitative analysis of very-low-voltage testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:332-337 [Conf]
  90. Jonathan T.-Y. Chang, Edward J. McCluskey
    SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:446-0 [Conf]
  91. Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey
    Experimental Results for IDDQ and VLV Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:118-125 [Conf]
  92. Erik Chmelar, Edward J. McCluskey
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:156-157 [Conf]
  93. Samy Makar, Edward J. McCluskey
    ATPG for scan chain latches and flip-flops. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:364-369 [Conf]
  94. Samy Makar, Edward J. McCluskey
    Checking experiments to test latches. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:196-201 [Conf]
  95. Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers
    Debating the Future of Burn-In. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:311-314 [Conf]
  96. Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, Francois-Fabien Ferhani, Edward Li, Subhasish Mitra
    ELF-Murphy Data on Defects and Test Sets. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:16-22 [Conf]
  97. Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey
    Effective TARO Pattern Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:161-166 [Conf]
  98. Subhasish Mitra, Edward J. McCluskey
    Word Voter: A New Voter Design for Triple Modular Redundant Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:465-470 [Conf]
  99. Subhasish Mitra, Edward J. McCluskey
    Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:178-183 [Conf]
  100. Subhasish Mitra, Edward J. McCluskey
    Design of Redundant Systems Protected Against Common-Mode Failures. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:190-197 [Conf]
  101. Subhasish Mitra, Edward J. McCluskey, Samy Makar
    Design for Testability and Testing of IEEE 1149.1 Tap Controller. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:247-252 [Conf]
  102. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    Fault Escapes in Duplex Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:453-458 [Conf]
  103. Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger
    Delay Defect Screening using Process Monitor Structures. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:43-52 [Conf]
  104. Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao
    An apparatus for pseudo-deterministic testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:125-131 [Conf]
  105. Robert B. Norwood, Edward J. McCluskey
    Synthesis-for-scan and scan chain ordering. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:87-92 [Conf]
  106. Robert B. Norwood, Edward J. McCluskey
    High-Level Synthesis for Orthogonal Sca. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:370-375 [Conf]
  107. Philip P. Shirvani, Edward J. McCluskey
    PADded Cache: A New Fault-Tolerance Technique for Cache Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:440-445 [Conf]
  108. Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure
    A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:154-170 [Conf]
  109. Nur A. Touba, Edward J. McCluskey
    Transformed pseudo-random patterns for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:410-416 [Conf]
  110. Nur A. Touba, Edward J. McCluskey
    Test point insertion based on path tracing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:2-8 [Conf]
  111. Nur A. Touba, Edward J. McCluskey
    Applying two-pattern tests using scan-mapping. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:393-399 [Conf]
  112. Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh
    MINVDD Testing for Weak CMOS ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:339-345 [Conf]
  113. Chao-Wen Tseng, James Li, Edward J. McCluskey
    Experimental Results for Slow-Speed Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:37-42 [Conf]
  114. Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson
    An Evaluation of Pseudo Random Testing for Detecting Real Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:404-410 [Conf]
  115. Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu
    Cold Delay Defect Screening. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:183-188 [Conf]
  116. Kyoung Youn Cho, Edward J. McCluskey
    Test Set Reordering Using the Gate Exhaustive Test Metric. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:199-204 [Conf]
  117. William F. Atchison, Samuel D. Conte, John W. Hamblen, Thomas E. Hull, Thomas A. Keenan, William B. Kehl, Edward J. McCluskey, Silvio O. Navarro, Werner C. Rheinboldt, Earl J. Schweppe, William Viavant, David M. Young
    Curriculum 68: Recommendations for academic programs in computer science: a report of the ACM curriculum committee on computer science. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1968, v:11, n:3, pp:151-197 [Journal]
  118. Edward J. McCluskey
    Design Techniques for Testable Embedded Error Checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:7, pp:84-88 [Journal]
  119. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    Efficient Multiplexer Synthesis Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:90-97 [Journal]
  120. Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey
    Reconfigurable Architecture for Autonomous Self-Repair. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:228-240 [Journal]
  121. Nirmal R. Saxena, Santiago Fernández-Gomez, Wei-Je Huang, Subhasish Mitra, Shu-Yi Yu, Edward J. McCluskey
    Dependable Computing and Online Testing in Adaptive and Configurable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:29-41 [Journal]
  122. Edward J. McCluskey
    Reduction of Feedback Loops in Sequential Circuits and Carry Leads in Iterative Networks [Citation Graph (0, 0)][DBLP]
    Information and Control, 1963, v:6, n:2, pp:99-118 [Journal]
  123. Daniel Boley, Gene H. Golub, Samy Makar, Nirmal R. Saxena, Edward J. McCluskey
    Floating Point Fault Tolerance with Backward Error Assertions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:2, pp:302-311 [Journal]
  124. Saied Bozorgui-Nesbat, Edward J. McCluskey
    Lower Overhead Design for Testability of Prgrammable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:379-383 [Journal]
  125. Cary K. Chin, Edward J. McCluskey
    Test Length for Pseudorandom Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:2, pp:252-256 [Journal]
  126. Tich T. Dao, Edward J. McCluskey, Lewis K. Russel
    Multivalued Integrated Injection Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1233-1241 [Journal]
  127. Hong Hao, Edward J. McCluskey
    Analysis of Gate Oxide Shorts in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:12, pp:1510-1516 [Journal]
  128. Ravishankar K. Iyer, Steven E. Butner, Edward J. McCluskey
    A Statistical Failure/Load Relationship: Results of a Multicomputer Study. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:7, pp:697-706 [Journal]
  129. Joseph L. A. Hughes, Edward J. McCluskey, David J. Lu
    Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:546-550 [Journal]
  130. Javad Khakbaz, Edward J. McCluskey
    Self-Testing Embedded Parity Checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:8, pp:753-756 [Journal]
  131. Edward J. McCluskey
    Logic Design of Multivalued I2L Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:8, pp:546-559 [Journal]
  132. Edward J. McCluskey
    Verification Testing - A Pseudoexhaustive Test Technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:541-546 [Journal]
  133. Edward J. McCluskey, Saied Bozorgui-Nesbat
    Design for Autonomous Test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:866-875 [Journal]
  134. Aamer Mahmood, Edward J. McCluskey
    Concurrent Error Detection Using Watchdog Processors - A Survey. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:2, pp:160-174 [Journal]
  135. Edward J. McCluskey, Kenneth P. Parker, John J. Shedletsky
    Boolean Network Probabilities and Network Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:2, pp:187-189 [Journal]
  136. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    A Design Diversity Metric and Analysis of Redundant Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:5, pp:498-510 [Journal]
  137. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    Efficient Design Diversity Estimation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1483-1492 [Journal]
  138. Nahmsuk Oh, Subhasish Mitra, Edward J. McCluskey
    ED4I: Error Detection by Diverse Data and Duplicated Instructions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:2, pp:180-199 [Journal]
  139. Kenneth P. Parker, Edward J. McCluskey
    Probabilistic Treatment of General Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:6, pp:668-670 [Journal]
  140. Kenneth P. Parker, Edward J. McCluskey
    Analysis of Logic Circuits with Faults Using Input Signal Probabilities. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:5, pp:573-578 [Journal]
  141. Kenneth P. Parker, Edward J. McCluskey
    Sequential Circuit Output Probabilities From Regular Expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:3, pp:222-231 [Journal]
  142. Nirmal R. Saxena, Piero Franco, Edward J. McCluskey
    Simple Bounds on Serial Signature Analysis Aliasing for Random Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:638-645 [Journal]
  143. Nirmal R. Saxena, Edward J. McCluskey
    Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:554-559 [Journal]
  144. Nirmal R. Saxena, Edward J. McCluskey
    Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:7, pp:969-975 [Journal]
  145. Nirmal R. Saxena, Edward J. McCluskey
    Counting Two-State Transition-Tour Sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:11, pp:1337-1342 [Journal]
  146. Nirmal R. Saxena, Edward J. McCluskey
    Parallel Signatur Analysis Design with Bounds on Aliasing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:4, pp:425-438 [Journal]
  147. Kenneth D. Wagner, Cary K. Chin, Edward J. McCluskey
    Pseudorandom Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:3, pp:332-343 [Journal]
  148. Laung-Terng Wang, Edward J. McCluskey
    Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:367-370 [Journal]
  149. Laung-Terng Wang, Edward J. McCluskey
    Linear Feedback Shift Register Design Using Cyclic Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:10, pp:1302-1306 [Journal]
  150. Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
    Optimized reseeding by seed ordering and encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:264-270 [Journal]
  151. Chien-Mo James Li, Edward J. McCluskey
    Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1748-1759 [Journal]
  152. Dick L. Liu, Edward J. McCluskey
    Design of large embedded CMOS PLAs for built-in self-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:50-59 [Journal]
  153. David J. Lu, Edward J. McCluskey
    Quantitative Evaluation of Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:2, pp:150-155 [Journal]
  154. Siyad C. Ma, Edward J. McCluskey
    Open faults in BiCMOS gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:567-575 [Journal]
  155. Edward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner
    Probability models for pseudorandom test sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:68-74 [Journal]
  156. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    An output encoding problem and a solution technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:761-768 [Journal]
  157. Nur A. Touba, Edward J. McCluskey
    Bit-fixing in pseudorandom sequences for scan BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:545-555 [Journal]
  158. Nur A. Touba, Edward J. McCluskey
    Logic synthesis of multilevel circuits with concurrent error detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:783-789 [Journal]
  159. Nur A. Touba, Edward J. McCluskey
    RP-SYN: synthesis of random pattern testable circuits with test point insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1202-1213 [Journal]
  160. Laung-Terng Wang, Edward J. McCluskey
    Hybrid designs generating maximum-length sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:91-99 [Journal]
  161. Laung-Terng Wang, Edward J. McCluskey
    Circuits for pseudoexhaustive test pattern generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1068-1080 [Journal]
  162. Ahmad A. Al-Yamani, Edward J. McCluskey
    Test chip experimental results on high-level structural test. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:4, pp:690-701 [Journal]
  163. Nirmal R. Saxena, Edward J. McCluskey
    Linear Complexity Assertions for Sorting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1994, v:20, n:6, pp:424-431 [Journal]

  164. University computer curricula. [Citation Graph (, )][DBLP]


  165. How Many Test Patterns are Useless? [Citation Graph (, )][DBLP]


  166. Error Sequence Analysis. [Citation Graph (, )][DBLP]


  167. Inconsistent Fail due to Limited Tester Timing Accuracy. [Citation Graph (, )][DBLP]


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