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Oliver Chiu-sing Choy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    A Totally Self-Checking Dynamic Asynchronous Datapath. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:27-32 [Conf]
  2. Pak-Kee Chan, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
    Card-Centric Framework - Providing I/O Resources for Smart Cards. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2004, pp:225-240 [Conf]
  3. Oliver Chiu-sing Choy, Tin-chak Pang, Juraj Povazanec, Cheong-fat Chan
    A Useful Micropipeline Architecture to Implement DSP Algorithms. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10212-0 [Conf]
  4. Lai-Kan Leung, Cheong-fat Chan, Oliver Chiu-sing Choy
    A giga-hertz CMOS digital controlled oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:610-613 [Conf]
  5. Wang-Chi Cheng, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    A 1.2 V 900 MHz CMOS mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:365-368 [Conf]
  6. Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    Pipelines in Dynamic Dual-Rail Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:701-710 [Conf]
  7. Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-ling Yang, Tin-yan Tang
    Pipelined Dataflow Architecture of a Small Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1217-1223 [Conf]
  8. Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    Design for Self-Checking and Self-Timed Datapath. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:417-430 [Conf]
  9. Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-fat Chan
    A New Control Circuit for Asynchronous Micropipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:9, pp:992-997 [Journal]
  10. Alex Wong, Kong-Pang Pun, Yuan-Ting Zhang, Oliver Chiu-sing Choy
    An ECG measurement IC using driven-right-leg circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  11. Pak-Keung Leung, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun
    An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  12. Wei Han, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    An efficient MFCC extraction method in speech recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  13. Xiao-Yong He, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-fat Chan
    A 0.5V fully differential OTA with local common feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  14. Siu-Kei Tang, Kong-Pang Pun, Oliver Chiu-sing Choy, Cheong-fat Chan
    A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. Chi-Hong Chan, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  16. Ke Xu, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun
    Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  17. Wei Han, Kwok-Wai Hon, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun
    A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:3, pp:223-232 [Journal]

  18. Active RC filter with reduced capacitance by current division technique. [Citation Graph (, )][DBLP]


  19. Adiabatic Smart Card. [Citation Graph (, )][DBLP]


  20. 0.8 V GPS band CMOS VCO with 29% Tuning Range. [Citation Graph (, )][DBLP]


  21. Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System. [Citation Graph (, )][DBLP]


  22. A 900 MHz 1.2 V CMOS mixer with high linearity. [Citation Graph (, )][DBLP]


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