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Publications of Author

1. Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs
   Analysis and Attenuation Proposal in Ground Bounce. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2004, pp:460-463 [Conf]
   
2. Víctor H. Champac, Antonio Rubio, Joan Figueras
   Analysis of the Floating Gate Defect in CMOS. [Citation Graph (0, 0)][DBLP]
   DFT, 1993, pp:101-108 [Conf]
   
3. Roberto Gomez, Alejandro Giron, Víctor H. Champac
   Test of Interconnection Opens Considering Coupling Signals. [Citation Graph (0, 0)][DBLP]
   DFT, 2005, pp:247-258 [Conf]
   
4. Fernando Mendoza-Hernandez, M. Linares, Víctor H. Champac, A. Diaz-Sanchez
   A new technique for noise-tolerant pipelined dynamic digital circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:185-188 [Conf]
   
5. Rosa Rodríguez-Montañés, J. A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio
   Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. [Citation Graph (0, 0)][DBLP]
   ITC, 1991, pp:510-519 [Conf]
   
6. Víctor H. Champac, Joan Figueras
   Testability of floating gate defects in sequential circuits. [Citation Graph (0, 0)][DBLP]
   VTS, 1995, pp:202-207 [Conf]
   
7. Víctor H. Champac, Antonio Zenteno
   Detectability Conditions for Interconnection Open Defect. [Citation Graph (0, 0)][DBLP]
   VTS, 2000, pp:305-312 [Conf]
   
8. Víctor H. Champac, José Castillejos, Joan Figueras
   IDDQ Testing of Opens in CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
   VTS, 1998, pp:106-111 [Conf]
   
9. Antonio Zenteno, Víctor H. Champac
   Resistive Opens in a Class of CMOS Latches: Analysis and DFT. [Citation Graph (0, 0)][DBLP]
   VTS, 2001, pp:138-144 [Conf]
   
10. Víctor H. Champac, Antonio Rubio, Joan Figueras
    Electrical model of the floating gate defect in CMOS ICs: implications on I_DDQ testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:359-369 [Journal]
    
11. Antonio Zenteno Ramirez, Guillermo Espinosa, Víctor H. Champac
    Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:572-577 [Journal]
    
12. 
    Programmable aging sensor for automotive safety-critical applications. [Citation Graph (, )][DBLP]
    
    
13. 
    Built-in aging monitoring for safety-critical applications. [Citation Graph (, )][DBLP]
    
    
14. 
    Detectability analysis of small delays due to resistive opens considering process variations. [Citation Graph (, )][DBLP]
    
    
15. 
    A design methodology for logic paths tolerant to local intra-die variations. [Citation Graph (, )][DBLP]
    
    
16. 
    Testing Skew and Logic Faults in SoC Interconnects. [Citation Graph (, )][DBLP]
    
    
17. 
    Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. [Citation Graph (, )][DBLP]