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Author:
Rajeev Alur: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajeev Alur, Thomas A. Henzinger
    Real-time Logics: Complexity and Expressiveness [Citation Graph (3, 0)][DBLP]
    LICS, 1990, pp:390-401 [Conf]
  2. Rajeev Alur, David L. Dill
    A Theory of Timed Automata. [Citation Graph (3, 0)][DBLP]
    Theor. Comput. Sci., 1994, v:126, n:2, pp:183-235 [Journal]
  3. Rajeev Alur, David L. Dill
    Automata For Modeling Real-Time Systems. [Citation Graph (1, 0)][DBLP]
    ICALP, 1990, pp:322-335 [Conf]
  4. Rajeev Alur, Thomas A. Henzinger
    Logics and Models of Real Time: A Survey. [Citation Graph (1, 0)][DBLP]
    REX Workshop, 1991, pp:74-106 [Conf]
  5. Rajeev Alur, Thomas A. Henzinger
    Real-Time Logics: Complexity and Expressiveness [Citation Graph (1, 0)][DBLP]
    Inf. Comput., 1993, v:104, n:1, pp:35-77 [Journal]
  6. Rajeev Alur
    Games for Formal Design and Verification of Reactive Systems. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:1- [Conf]
  7. Wonhong Nam, Rajeev Alur
    Learning-Based Symbolic Assume-Guarantee Reasoning with Automatic Decomposition. [Citation Graph (0, 0)][DBLP]
    ATVA, 2006, pp:170-185 [Conf]
  8. Rajeev Alur
    Formal Analysis of Hierarchical State Machines. [Citation Graph (0, 0)][DBLP]
    Verification: Theory and Practice, 2003, pp:42-66 [Conf]
  9. Alwyn Goodloe, Michael McDougall, Carl A. Gunter, Rajeev Alur
    Predictable programs in barcodes. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:298-303 [Conf]
  10. Rajeev Alur
    Timed Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 1999, pp:8-22 [Conf]
  11. Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani
    Partial-Order Reduction in Symbolic State Space Exploration. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:340-351 [Conf]
  12. Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger
    Computing Accumulated Delays in Real-time Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1993, pp:181-193 [Conf]
  13. Rajeev Alur, Swarat Chaudhuri, P. Madhusudan
    Languages of Nested Trees. [Citation Graph (0, 0)][DBLP]
    CAV, 2006, pp:329-342 [Conf]
  14. Rajeev Alur, Kousha Etessami, Mihalis Yannakakis
    Analysis of Recursive State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:207-220 [Conf]
  15. Rajeev Alur, Limor Fix, Thomas A. Henzinger
    A Determinizable Class of Timed Automata. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:1-13 [Conf]
  16. Rajeev Alur, Radu Grosu, Michael McDougall
    Efficient Reachability Analysis of Hierarchical Reactive Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 2000, pp:280-295 [Conf]
  17. Rajeev Alur, Thomas A. Henzinger
    Local Liveness for Compositional Modeling of Fair Reactive Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:166-179 [Conf]
  18. Rajeev Alur, Thomas A. Henzinger, Freddy Y. C. Mang, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran
    MOCHA: Modularity in Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:521-525 [Conf]
  19. Rajeev Alur, Alon Itai, Robert P. Kurshan, Mihalis Yannakakis
    Timing Verification by Successive Approximation. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:137-150 [Conf]
  20. Rajeev Alur, P. Madhusudan, Wonhong Nam
    Symbolic Compositional Verification by Learning Assumptions. [Citation Graph (0, 0)][DBLP]
    CAV, 2005, pp:548-562 [Conf]
  21. Rajeev Alur, Michael McDougall, Zijiang Yang
    Exploiting Behavioral Hierarchy for Efficient Model Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:338-342 [Conf]
  22. Rajeev Alur, Salvatore La Torre, P. Madhusudan
    Modular Strategies for Infinite Games on Recursive Graphs. [Citation Graph (0, 0)][DBLP]
    CAV, 2003, pp:67-79 [Conf]
  23. Rajeev Alur, Bow-Yaw Wang
    Verifying Network Protocol Implementations by Symbolic Refinement Checking. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:169-181 [Conf]
  24. Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin
    Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study. [Citation Graph (0, 0)][DBLP]
    CAV, 2006, pp:489-502 [Conf]
  25. M. Oliver Möller, Rajeev Alur
    Heuristics for Hierarchical Partitioning with Application to Model Checking. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:71-85 [Conf]
  26. Rajeev Alur, Thomas A. Henzinger, Orna Kupferman
    Alternating-Time Temporal Logic. [Citation Graph (0, 0)][DBLP]
    COMPOS, 1997, pp:23-60 [Conf]
  27. Rajeev Alur
    Exploiting Hierarchical Structure for Efficient Formal Verification. [Citation Graph (0, 0)][DBLP]
    CONCUR, 2000, pp:66-68 [Conf]
  28. Rajeev Alur
    The Benefits of Exposing Calls and Returns. [Citation Graph (0, 0)][DBLP]
    CONCUR, 2005, pp:2-3 [Conf]
  29. Rajeev Alur, Luca de Alfaro, Thomas A. Henzinger, Freddy Y. C. Mang
    Automating Modular Verification. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1999, pp:82-97 [Conf]
  30. Rajeev Alur, Swarat Chaudhuri, Kousha Etessami, Sudipto Guha, Mihalis Yannakakis
    Compression of Partially Ordered Strings. [Citation Graph (0, 0)][DBLP]
    CONCUR, 2003, pp:42-56 [Conf]
  31. Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger
    The Observational Power of Clocks. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1994, pp:162-177 [Conf]
  32. Rajeev Alur, Costas Courcoubetis, Nicolas Halbwachs, David L. Dill, Howard Wong-Toi
    Minimization of Timed Transition Systems. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1992, pp:340-354 [Conf]
  33. Rajeev Alur, Thomas A. Henzinger
    Modularity for Timed and Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1997, pp:74-88 [Conf]
  34. Rajeev Alur, Thomas A. Henzinger, Orna Kupferman, Moshe Y. Vardi
    Alternating Refinement Relations. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1998, pp:163-178 [Conf]
  35. Rajeev Alur, Salvatore La Torre, P. Madhusudan
    Playing Games with Boxes and Diamonds. [Citation Graph (0, 0)][DBLP]
    CONCUR, 2003, pp:127-141 [Conf]
  36. Rajeev Alur, Bow-Yaw Wang
    ``Next'' Heuristic for On-the-Fly Model Checking. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1999, pp:98-113 [Conf]
  37. Rajeev Alur, Mihalis Yannakakis
    Model Checking of Message Sequence Charts. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1999, pp:114-129 [Conf]
  38. Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton
    Verifying Abstractions of Timed Systems. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1996, pp:546-562 [Conf]
  39. Rajeev Alur, P. Madhusudan
    Adding Nesting Structure to Words. [Citation Graph (0, 0)][DBLP]
    Developments in Language Theory, 2006, pp:1-13 [Conf]
  40. Rajeev Alur, Thao Dang, Joel M. Esposito, Rafael B. Fierro, Yerang Hur, Franjo Ivancic, Vijay Kumar, Insup Lee, Pradyumna Mishra, George J. Pappas, Oleg Sokolsky
    Hierarchical Hybrid Modeling of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2001, pp:14-31 [Conf]
  41. Michael McDougall, Rajeev Alur, Carl A. Gunter
    A model-based approach to integrating security policies for embedded devices. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:211-219 [Conf]
  42. Truong Nghiem, George J. Pappas, Rajeev Alur, Antoine Girard
    Time-triggered implementations of dynamic controllers. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:2-11 [Conf]
  43. Allen D. Malony, Rajeev Alur
    Performance Evaluation and Prediction. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:191-192 [Conf]
  44. Rajeev Alur, Joel M. Esposito, M. Kim, Vijay Kumar, Insup Lee
    Formal Modeling and Analysis of Hybrid Systems: A Case Study in Multi-robot Coordination. [Citation Graph (0, 0)][DBLP]
    World Congress on Formal Methods, 1999, pp:212-232 [Conf]
  45. Rajeev Alur, Radu Grosu, Bow-Yaw Wang
    Automated Refinement Checking for Asynchronous Processes. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:55-72 [Conf]
  46. Zijiang Yang, Rajeev Alur
    Variable Reuse for Efficient Image Computation. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:430-444 [Conf]
  47. Rajeev Alur, Thomas A. Henzinger
    A Really Temporal Logic [Citation Graph (0, 0)][DBLP]
    FOCS, 1989, pp:164-169 [Conf]
  48. Rajeev Alur, Thomas A. Henzinger
    Back to the Future: Towards a Theory of Timed Regular Languages [Citation Graph (0, 0)][DBLP]
    FOCS, 1992, pp:177-186 [Conf]
  49. Rajeev Alur, Thomas A. Henzinger, Orna Kupferman
    Alternating-time Temporal Logic. [Citation Graph (0, 0)][DBLP]
    FOCS, 1997, pp:100-109 [Conf]
  50. Mikhail Bernadsky, Raman Sharykin, Rajeev Alur
    Structured Modeling of Concurrent Stochastic Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    FORMATS/FTRTFT, 2004, pp:309-324 [Conf]
  51. Rajeev Alur
    Efficient Formal Verification of Hierarchical Descriptions. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1998, pp:269- [Conf]
  52. Rajeev Alur, Swarat Chaudhuri
    Branching Pushdown Tree Automata. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 2006, pp:393-404 [Conf]
  53. Rajeev Alur, Calin Belta, Franjo Ivancic, Vijay Kumar, Harvey Rubin, Jonathan Schug, Oleg Sokolsky, Jonathan Webb
    Visual Programming for Modeling and Simulation of Biomolecular Regulatory Networks. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:702-712 [Conf]
  54. Rajeev Alur, Mikhail Bernadsky
    Bounded Model Checking for GSMP Models of Stochastic Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    HSCC, 2006, pp:19-33 [Conf]
  55. Rajeev Alur, Calin Belta, Franjo Ivancic
    Hybrid Modeling and Simulation of Biomolecular Networks. [Citation Graph (0, 0)][DBLP]
    HSCC, 2001, pp:19-32 [Conf]
  56. Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger, Pei-Hsin Ho
    Hybrid Automata: An Algorithmic Approach to the Specification and Verification of Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    Hybrid Systems, 1992, pp:209-229 [Conf]
  57. Rajeev Alur, Thao Dang, Franjo Ivancic
    Reachability Analysis of Hybrid Systems via Predicate Abstraction. [Citation Graph (0, 0)][DBLP]
    HSCC, 2002, pp:35-48 [Conf]
  58. Rajeev Alur, Thao Dang, Franjo Ivancic
    Progress on Reachability Analysis of Hybrid Systems Using Predicate Abstraction. [Citation Graph (0, 0)][DBLP]
    HSCC, 2003, pp:4-19 [Conf]
  59. Rajeev Alur, Radu Grosu, Yerang Hur, Vijay Kumar, Insup Lee
    Modular Specification of Hybrid Systems in CHARON. [Citation Graph (0, 0)][DBLP]
    HSCC, 2000, pp:6-19 [Conf]
  60. Rajeev Alur, Radu Grosu, Insup Lee, Oleg Sokolsky
    Compositional Refinement for Hierarchical Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    HSCC, 2001, pp:33-48 [Conf]
  61. Rajeev Alur, Robert P. Kurshan
    Timing Analysis in COSPAN. [Citation Graph (0, 0)][DBLP]
    Hybrid Systems, 1995, pp:220-231 [Conf]
  62. Rajeev Alur, Sampath Kannan, Salvatore La Torre
    Polyhedral Flows in Hybrid Automata. [Citation Graph (0, 0)][DBLP]
    HSCC, 1999, pp:5-18 [Conf]
  63. Rajeev Alur, Salvatore La Torre, P. Madhusudan
    Perturbed Timed Automata. [Citation Graph (0, 0)][DBLP]
    HSCC, 2005, pp:70-85 [Conf]
  64. Rajeev Alur, Salvatore La Torre, George J. Pappas
    Optimal Paths in Weighted Timed Automata. [Citation Graph (0, 0)][DBLP]
    HSCC, 2001, pp:49-62 [Conf]
  65. Gera Weiss, Rajeev Alur
    Automata Based Interfaces for Control and Scheduling. [Citation Graph (0, 0)][DBLP]
    HSCC, 2007, pp:601-613 [Conf]
  66. Mikhail Bernadsky, Rajeev Alur
    Symbolic Analysis for GSMP Models with One Stateful Clock. [Citation Graph (0, 0)][DBLP]
    HSCC, 2007, pp:90-103 [Conf]
  67. Rajeev Alur, Mikhail Bernadsky, P. Madhusudan
    Optimal Reachability for Weighted Timed Games. [Citation Graph (0, 0)][DBLP]
    ICALP, 2004, pp:122-133 [Conf]
  68. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Model-Checking for Probabilistic Real-Time Systems (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    ICALP, 1991, pp:115-126 [Conf]
  69. Rajeev Alur, Pavol Cerný, Steve Zdancewic
    Preserving Secrecy Under Refinement. [Citation Graph (0, 0)][DBLP]
    ICALP (2), 2006, pp:107-118 [Conf]
  70. Rajeev Alur, Kousha Etessami, Mihalis Yannakakis
    Realizability and Verification of MSC Graphs. [Citation Graph (0, 0)][DBLP]
    ICALP, 2001, pp:797-808 [Conf]
  71. Rajeev Alur, Viraj Kumar, P. Madhusudan, Mahesh Viswanathan
    Congruences for Visibly Pushdown Languages. [Citation Graph (0, 0)][DBLP]
    ICALP, 2005, pp:1102-1114 [Conf]
  72. Rajeev Alur, Sampath Kannan, Mihalis Yannakakis
    Communicating Hierarchical State Machines. [Citation Graph (0, 0)][DBLP]
    ICALP, 1999, pp:169-178 [Conf]
  73. Rajeev Alur, Kenneth L. McMillan, Doron Peled
    Deciding Global Partial-Order Properties. [Citation Graph (0, 0)][DBLP]
    ICALP, 1998, pp:41-52 [Conf]
  74. Rajeev Alur, Kousha Etessami, Salvatore La Torre, Doron Peled
    Parametric Temporal Logic for "Model Measuring". [Citation Graph (0, 0)][DBLP]
    ICALP, 1999, pp:159-168 [Conf]
  75. Rajeev Alur, Luca de Alfaro, Radu Grosu, Thomas A. Henzinger, M. Kang, Christoph M. Kirsch, Rupak Majumdar, Freddy Y. C. Mang, Bow-Yaw Wang
    JMOCHA: A Model Checking Tool that Exploits Design Structure. [Citation Graph (0, 0)][DBLP]
    ICSE, 2001, pp:835-836 [Conf]
  76. Rajeev Alur, Kousha Etessami, Mihalis Yannakakis
    Inference of message sequence charts. [Citation Graph (0, 0)][DBLP]
    ICSE, 2000, pp:304-313 [Conf]
  77. Rajeev Alur, Lalita Jategaonkar Jagadeesan, Joseph J. Kott, James Von Olnhausen
    Model-Checking of Real-Time Systems: A Telecommunications Application (Experience Report). [Citation Graph (0, 0)][DBLP]
    ICSE, 1997, pp:514-524 [Conf]
  78. Rajeev Alur, Aveek K. Das, Joel M. Esposito, Rafael B. Fierro, Gregory Z. Grudic, Yerang Hur, Vijay Kumar, Insup Lee, J. P. Lee, James P. Ostrowski, George J. Pappas, Ben Southall, John R. Spletzer, Camillo J. Taylor
    A Framework and Architecture for Multirobot Coordination. [Citation Graph (0, 0)][DBLP]
    ISER, 2000, pp:303-312 [Conf]
  79. Rajeev Alur, Radu Grosu
    Shared Variables Interaction Diagrams. [Citation Graph (0, 0)][DBLP]
    ASE, 2001, pp:281-288 [Conf]
  80. Rajeev Alur, Franjo Ivancic, Jesung Kim, Insup Lee, Oleg Sokolsky
    Generating embedded software from hierarchical hybrid models. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:171-182 [Conf]
  81. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Model-Checking for Real-Time Systems [Citation Graph (0, 0)][DBLP]
    LICS, 1990, pp:414-425 [Conf]
  82. Rajeev Alur, Thomas A. Henzinger
    Finitary Fairness [Citation Graph (0, 0)][DBLP]
    LICS, 1994, pp:52-61 [Conf]
  83. Rajeev Alur, Thomas A. Henzinger
    Reactive Modules. [Citation Graph (0, 0)][DBLP]
    LICS, 1996, pp:207-218 [Conf]
  84. Rajeev Alur, Kenneth L. McMillan, Doron Peled
    Model-Checking of Correctness Conditions for Concurrent Objects. [Citation Graph (0, 0)][DBLP]
    LICS, 1996, pp:219-228 [Conf]
  85. Rajeev Alur, Doron Peled, Wojciech Penczek
    Model-Checking of Causality Properties [Citation Graph (0, 0)][DBLP]
    LICS, 1995, pp:90-100 [Conf]
  86. Rajeev Alur, Salvatore La Torre
    Deterministic Generators and Games for LTL Fragments. [Citation Graph (0, 0)][DBLP]
    LICS, 2001, pp:291-302 [Conf]
  87. Rajeev Alur, Tomás Feder, Thomas A. Henzinger
    The Benefits of Relaxing Punctuality. [Citation Graph (0, 0)][DBLP]
    PODC, 1991, pp:139-152 [Conf]
  88. Rajeev Alur, Gadi Taubenfeld
    Contention-free Complexity of Shared Memory Algorithms. [Citation Graph (0, 0)][DBLP]
    PODC, 1994, pp:61-70 [Conf]
  89. Rajeev Alur, Swarat Chaudhuri, P. Madhusudan
    A fixpoint calculus for local and global program flows. [Citation Graph (0, 0)][DBLP]
    POPL, 2006, pp:153-165 [Conf]
  90. Rajeev Alur, Pavol Cerný, P. Madhusudan, Wonhong Nam
    Synthesis of interface specifications for Java classes. [Citation Graph (0, 0)][DBLP]
    POPL, 2005, pp:98-109 [Conf]
  91. Rajeev Alur, Radu Grosu
    Modular Refinement of Hierarchic Reactive Machines. [Citation Graph (0, 0)][DBLP]
    POPL, 2000, pp:390-402 [Conf]
  92. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Verifying Automata Specifications of Probabilistic Real-time Systems. [Citation Graph (0, 0)][DBLP]
    REX Workshop, 1991, pp:28-44 [Conf]
  93. Rajeev Alur, David L. Dill
    The Theory of Timed Automata. [Citation Graph (0, 0)][DBLP]
    REX Workshop, 1991, pp:45-73 [Conf]
  94. Rajeev Alur, Arun Chandrashekharapuram
    Dispatch Sequences for Embedded Control Models. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2005, pp:508-518 [Conf]
  95. Rajeev Alur, Thomas A. Henzinger, Pei-Hsin Ho
    Automatic Symbolic Verification of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1993, pp:2-11 [Conf]
  96. Rajeev Alur, Robert P. Kurshan, Mahesh Viswanathan
    Membership Questions for Timed and Hybrid Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1998, pp:254-263 [Conf]
  97. Rajeev Alur, Gadi Taubenfeld
    Results about Fast Mutual Exclusion. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1992, pp:12-22 [Conf]
  98. Hakan Yazarel, Antoine Girard, George J. Pappas, Rajeev Alur
    Quantifying the Gap between Embedded Control Models and Time-Triggered Implementations. [Citation Graph (0, 0)][DBLP]
    RTSS, 2005, pp:111-120 [Conf]
  99. Rajeev Alur, P. Madhusudan
    Decision Problems for Timed Automata: A Survey. [Citation Graph (0, 0)][DBLP]
    SFM, 2004, pp:1-24 [Conf]
  100. Rajeev Alur, Mihalis Yannakakis
    Model Checking of Hierarchical State Machines. [Citation Graph (0, 0)][DBLP]
    SIGSOFT FSE, 1998, pp:175-188 [Conf]
  101. Rajeev Alur, Gadi Taubenfeld
    How to Share an Object: A Fast Timing-Based Solution. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:470-477 [Conf]
  102. Rajeev Alur, Hagit Attiya, Gadi Taubenfeld
    Time-adaptive algorithms for synchronization. [Citation Graph (0, 0)][DBLP]
    STOC, 1994, pp:800-809 [Conf]
  103. Rajeev Alur, Costas Courcoubetis, Mihalis Yannakakis
    Distinguishing tests for nondeterministic and probabilistic machines. [Citation Graph (0, 0)][DBLP]
    STOC, 1995, pp:363-372 [Conf]
  104. Rajeev Alur, Thomas A. Henzinger, Moshe Y. Vardi
    Parametric real-time reasoning. [Citation Graph (0, 0)][DBLP]
    STOC, 1993, pp:592-601 [Conf]
  105. Rajeev Alur, P. Madhusudan
    Visibly pushdown languages. [Citation Graph (0, 0)][DBLP]
    STOC, 2004, pp:202-211 [Conf]
  106. Rajeev Alur, Swarat Chaudhuri, Kousha Etessami, P. Madhusudan
    On-the-Fly Reachability and Cycle Detection for Recursive State Machines. [Citation Graph (0, 0)][DBLP]
    TACAS, 2005, pp:61-76 [Conf]
  107. Rajeev Alur, Thao Dang, Franjo Ivancic
    Counter-Example Guided Predicate Abstraction of Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    TACAS, 2003, pp:208-223 [Conf]
  108. Rajeev Alur, Kousha Etessami, P. Madhusudan
    A Temporal Logic of Nested Calls and Returns. [Citation Graph (0, 0)][DBLP]
    TACAS, 2004, pp:467-481 [Conf]
  109. Rajeev Alur, Gerard J. Holzmann, Doron Peled
    An Analyser for Mesage Sequence Charts. [Citation Graph (0, 0)][DBLP]
    TACAS, 1996, pp:35-48 [Conf]
  110. Rajeev Alur, Thomas A. Henzinger, Sriram K. Rajamani
    Symbolic Exploration of transition Hierarchies. [Citation Graph (0, 0)][DBLP]
    TACAS, 1998, pp:330-344 [Conf]
  111. Rajeev Alur, Salvatore La Torre, P. Madhusudan
    Modular Strategies for Recursive Game Graphs. [Citation Graph (0, 0)][DBLP]
    TACAS, 2003, pp:363-378 [Conf]
  112. Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin
    Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement. [Citation Graph (0, 0)][DBLP]
    VMCAI, 2005, pp:130-145 [Conf]
  113. Rajeev Alur
    Next Steps in Formal Verification. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:4es, pp:115- [Journal]
  114. Rajeev Alur, Gadi Taubenfeld
    Fast Timing-Based Algorithms. [Citation Graph (0, 0)][DBLP]
    Distributed Computing, 1996, v:10, n:1, pp:1-10 [Journal]
  115. P. Madhusudan, Wonhong Nam, Rajeev Alur
    Symbolic computational techniques for solving games. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2003, v:89, n:4, pp:- [Journal]
  116. Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani
    Partial-Order Reduction in Symbolic State-Space Exploration. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2001, v:18, n:2, pp:97-116 [Journal]
  117. Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger
    Computing Accumulated Delays in Real-time Systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:11, n:2, pp:137-155 [Journal]
  118. Rajeev Alur, Thomas A. Henzinger
    Introduction. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1999, v:14, n:3, pp:235- [Journal]
  119. Rajeev Alur, Thomas A. Henzinger
    Introduction. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1999, v:15, n:1, pp:5- [Journal]
  120. Rajeev Alur, Thomas A. Henzinger
    Reactive Modules. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1999, v:15, n:1, pp:7-48 [Journal]
  121. Rajeev Alur, Sampath Kannan, Salvatore La Torre
    Polyhedral Flows in Hybrid Automata. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2004, v:24, n:3, pp:261-280 [Journal]
  122. Rajeev Alur, Kenneth L. McMillan, Doron Peled
    Deciding Global Partial-Order Properties. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2005, v:26, n:1, pp:7-25 [Journal]
  123. Rajeev Alur, Costas Courcoubetis, David L. Dill
    Model-Checking in Dense Real-time [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1993, v:104, n:1, pp:2-34 [Journal]
  124. Rajeev Alur, Thomas A. Henzinger
    Introduction. [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 2001, v:164, n:2, pp:233- [Journal]
  125. Rajeev Alur, Alon Itai, Robert P. Kurshan, Mihalis Yannakakis
    Timing Verification by Successive Approximation [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1995, v:118, n:1, pp:142-157 [Journal]
  126. Rajeev Alur, Kenneth L. McMillan, Doron Peled
    Model-Checking of Correctness Conditions for Concurrent Objects. [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 2000, v:160, n:1-2, pp:167-188 [Journal]
  127. Rajeev Alur, Gadi Taubenfeld
    Contention-Free Complexity of Shared Memory Algorithms. [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 1996, v:126, n:1, pp:62-73 [Journal]
  128. Rafael B. Fierro, Aveek K. Das, John R. Spletzer, Joel M. Esposito, Vijay Kumar, James P. Ostrowski, George J. Pappas, Camillo J. Taylor, Yerang Hur, Rajeev Alur, Insup Lee, Gregory Z. Grudic, Ben Southall
    A Framework and Architecture for Multi-Robot Coordination. [Citation Graph (0, 0)][DBLP]
    I. J. Robotic Res., 2002, v:21, n:10-11, pp:977-998 [Journal]
  129. Rajeev Alur, Doron Peled
    Undecidability of Partial Order Logics. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1999, v:69, n:3, pp:137-143 [Journal]
  130. Rajeev Alur, Tomás Feder, Thomas A. Henzinger
    The Benefits of Relaxing Punctuality. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1996, v:43, n:1, pp:116-146 [Journal]
  131. Rajeev Alur, Thomas A. Henzinger
    A Really Temporal Logic. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1994, v:41, n:1, pp:181-204 [Journal]
  132. Rajeev Alur, Thomas A. Henzinger, Orna Kupferman
    Alternating-time temporal logic. [Citation Graph (0, 0)][DBLP]
    J. ACM, 2002, v:49, n:5, pp:672-713 [Journal]
  133. Rajeev Alur, Arun Chandrashekharapuram
    Dispatch sequences for embedded control models. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 2007, v:73, n:2, pp:156-170 [Journal]
  134. Rajeev Alur, Radu Grosu, Insup Lee, Oleg Sokolsky
    Compositional modeling and refinement for hierarchical hybrid systems. [Citation Graph (0, 0)][DBLP]
    J. Log. Algebr. Program., 2006, v:68, n:1-2, pp:105-128 [Journal]
  135. Rajeev Alur, Thao Dang, Joel M. Esposito, Yerang Hur, Franjo Ivancic, Vijay Kumar, Insup Lee, Pradyumna Mishra, George J. Pappas, Oleg Sokolsky
    Hierarchical modeling and analysis of embedded systems. [Citation Graph (0, 0)][DBLP]
    Proceedings of the IEEE, 2003, v:91, n:1, pp:11-28 [Journal]
  136. Rajeev Alur, Hagit Attiya, Gadi Taubenfeld
    Time-Adaptive Algorithms for Synchronization. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1997, v:26, n:2, pp:539-556 [Journal]
  137. Rajeev Alur, Gerard J. Holzmann, Doron Peled
    An Analyzer for Message Sequence Charts. [Citation Graph (0, 0)][DBLP]
    Software - Concepts and Tools, 1996, v:17, n:2, pp:70-77 [Journal]
  138. Rajeev Alur, David Arney, Elsa L. Gunter, Insup Lee, Jaime Lee, Wonhong Nam, Frederick Pearce, Stephen Van Albert, Jiaxiang Zhou
    Formal specifications and analysis of the computer-assisted resuscitation algorithm (CARA) Infusion Pump Control System. [Citation Graph (0, 0)][DBLP]
    STTT, 2004, v:5, n:4, pp:308-319 [Journal]
  139. Rajeev Alur, Thomas A. Henzinger
    Real-Time System = Discrete System + Clock Variables. [Citation Graph (0, 0)][DBLP]
    STTT, 1997, v:1, n:1-2, pp:86-109 [Journal]
  140. Rajeev Alur, P. Madhusudan, Wonhong Nam
    Symbolic computational techniques for solving games. [Citation Graph (0, 0)][DBLP]
    STTT, 2005, v:7, n:2, pp:118-128 [Journal]
  141. Rajeev Alur, Costas Courcoubetis, Nicolas Halbwachs, Thomas A. Henzinger, Pei-Hsin Ho, Xavier Nicollin, Alfredo Olivero, Joseph Sifakis, Sergio Yovine
    The Algorithmic Analysis of Hybrid Systems. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1995, v:138, n:1, pp:3-34 [Journal]
  142. Rajeev Alur, Thao Dang, Franjo Ivancic
    Counterexample-guided predicate abstraction of hybrid systems. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2006, v:354, n:2, pp:250-271 [Journal]
  143. Rajeev Alur, Kousha Etessami, Mihalis Yannakakis
    Realizability and verification of MSC graphs. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2005, v:331, n:1, pp:97-114 [Journal]
  144. Rajeev Alur, Limor Fix, Thomas A. Henzinger
    Event-Clock Automata: A Determinizable Class of Timed Automata. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1999, v:211, n:1-2, pp:253-273 [Journal]
  145. Rajeev Alur, Salvatore La Torre, P. Madhusudan
    Modular strategies for recursive game graphs. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2006, v:354, n:2, pp:230-249 [Journal]
  146. Rajeev Alur, Salvatore La Torre, George J. Pappas
    Optimal paths in weighted timed automata. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2004, v:318, n:3, pp:297-322 [Journal]
  147. Rajeev Alur, Insup Lee
    Preface. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:4, pp:707- [Journal]
  148. Rajeev Alur, Thao Dang, Franjo Ivancic
    Predicate abstraction for reachability analysis of hybrid systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:152-199 [Journal]
  149. Rajeev Alur, Kousha Etessami, Salvatore La Torre, Doron Peled
    Parametric temporal logic for "model measuring". [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Log., 2001, v:2, n:3, pp:388-407 [Journal]
  150. Rajeev Alur, Salvatore La Torre
    Deterministic generators and games for Ltl fragments. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Log., 2004, v:5, n:1, pp:1-25 [Journal]
  151. Rajeev Alur, Michael Benedikt, Kousha Etessami, Patrice Godefroid, Thomas W. Reps, Mihalis Yannakakis
    Analysis of recursive state machines. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2005, v:27, n:4, pp:786-818 [Journal]
  152. Rajeev Alur, Radu Grosu
    Modular refinement of hierarchic reactive machines. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2004, v:26, n:2, pp:339-369 [Journal]
  153. Rajeev Alur, Thomas A. Henzinger
    Finitary Fairness. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1998, v:20, n:6, pp:1171-1194 [Journal]
  154. Rajeev Alur, Mihalis Yannakakis
    Model checking of hierarchical state machines. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2001, v:23, n:3, pp:273-303 [Journal]
  155. Rajeev Alur, Kousha Etessami, Mihalis Yannakakis
    Inference of Message Sequence Charts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2003, v:29, n:7, pp:623-633 [Journal]
  156. Rajeev Alur, Thomas A. Henzinger, Pei-Hsin Ho
    Automatic Symbolic Verification of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1996, v:22, n:3, pp:181-201 [Journal]
  157. Rajeev Alur
    Marrying Words and Trees. [Citation Graph (0, 0)][DBLP]
    CSR, 2007, pp:5- [Conf]
  158. Rajeev Alur, Marcelo Arenas, Pablo Barceló, Kousha Etessami, Neil Immerman, Leonid Libkin
    First-Order and Temporal Logics for Nested Words. [Citation Graph (0, 0)][DBLP]
    LICS, 2007, pp:151-160 [Conf]
  159. Rajeev Alur
    Games for formal design and verification of reactive systems. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:3- [Conf]
  160. Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin
    CheckFence: checking consistency of concurrent data types on relaxed memory models. [Citation Graph (0, 0)][DBLP]
    PLDI, 2007, pp:12-21 [Conf]
  161. Rajeev Alur
    Marrying words and trees. [Citation Graph (0, 0)][DBLP]
    PODS, 2007, pp:233-242 [Conf]
  162. Swarat Chaudhuri, Rajeev Alur
    Instrumenting C Programs with Nested Word Monitors. [Citation Graph (0, 0)][DBLP]
    SPIN, 2007, pp:279-283 [Conf]
  163. Rajeev Alur, Pavol Cerný, Swarat Chaudhuri
    Model Checking on Trees with Path Equivalences. [Citation Graph (0, 0)][DBLP]
    TACAS, 2007, pp:664-678 [Conf]

  164. Marrying Words and Trees. [Citation Graph (, )][DBLP]


  165. Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models. [Citation Graph (, )][DBLP]


  166. Ranking Automata and Games for Prioritized Requirements. [Citation Graph (, )][DBLP]


  167. Automated Analysis of Java Methods for Confidentiality. [Citation Graph (, )][DBLP]


  168. Generating Litmus Tests for Contrasting Memory Consistency Models. [Citation Graph (, )][DBLP]


  169. Model Checking of Linearizability of Concurrent List Implementations. [Citation Graph (, )][DBLP]


  170. Algorithmic Analysis of Array-Accessing Programs. [Citation Graph (, )][DBLP]


  171. RTComposer: a framework for real-time components with scheduling interfaces. [Citation Graph (, )][DBLP]


  172. Symbolic analysis for improving simulation coverage of Simulink/Stateflow models. [Citation Graph (, )][DBLP]


  173. Temporal Reasoning about Program Executions. [Citation Graph (, )][DBLP]


  174. On Omega-Languages Defined by Mean-Payoff Conditions. [Citation Graph (, )][DBLP]


  175. Specification and Analysis of Network Resource Requirements of Control Systems. [Citation Graph (, )][DBLP]


  176. Regular Specifications of Resource Requirements for Embedded Control Software. [Citation Graph (, )][DBLP]


  177. Modeling and Analysis of Multi-hop Control Networks. [Citation Graph (, )][DBLP]


  178. An implementation of three algorithms for timing verification based on automata emptiness. [Citation Graph (, )][DBLP]


  179. Model Checking: From Tools to Theory. [Citation Graph (, )][DBLP]


  180. Temporal Reasoning for Procedural Programs. [Citation Graph (, )][DBLP]


  181. Trends and Challenges in Algorithmic Software Verification. [Citation Graph (, )][DBLP]


  182. Robust stability of multi-hop control networks. [Citation Graph (, )][DBLP]


  183. First-Order and Temporal Logics for Nested Words [Citation Graph (, )][DBLP]


  184. Algorithmic Verification of Single-Pass List Processing Programs [Citation Graph (, )][DBLP]


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