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Publications of Author

1. Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
   Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas. [Citation Graph (0, 0)][DBLP]
   ATVA, 2004, pp:108-119 [Conf]
   
2. Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
   Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction. [Citation Graph (0, 0)][DBLP]
   COCOON, 2000, pp:467-476 [Conf]
   
3. Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara
   Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2000, pp:455-469 [Conf]
   
4. Toshinobu Kashiwabara
   Algorithms for some intersection graphs. [Citation Graph (0, 0)][DBLP]
   Graph Theory and Algorithms, 1980, pp:171-181 [Conf]
   
5. Toshinobu Kashiwabara, Sumio Masuda, Kazuo Nakajima, Toshio Fujisawa
   Generation of Maximum Independent Sets of a Bipartite Graph and Maximum Cliques of a Circular-Arc Graph. [Citation Graph (0, 0)][DBLP]
   J. Algorithms, 1992, v:13, n:1, pp:161-174 [Journal]
   
6. Tatsuo Ohtsuki, Hajimu Mori, Toshinobu Kashiwabara, Toshio Fujisawa
   On Minimal Augmentation of a Graph to Obtain an Interval Graph. [Citation Graph (0, 0)][DBLP]
   J. Comput. Syst. Sci., 1981, v:22, n:1, pp:60-97 [Journal]
   
7. Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Thio Fujisawa
   Crossing Minimization in Linear Embeddings of Graphs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:1, pp:124-127 [Journal]
   
8. Chong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima
   Exact algorithms for multilayer topological via minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1165-1173 [Journal]
   
9. 
   Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. [Citation Graph (, )][DBLP]
   
   
10. 
    Automatic monitor generation from regular expression based specifications for module interface verification. [Citation Graph (, )][DBLP]