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Kai-Hui Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo
    A Temporal Assertion Extension to Verilog. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:499-504 [Conf]
  2. Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo
    Automatic Partitioner for Behavior Level Distributed Logic Simulation. [Citation Graph (0, 0)][DBLP]
    FORTE, 2005, pp:525-528 [Conf]
  3. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
    Simulation-based bug trace minimization with BMC-based refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1045-1051 [Conf]
  4. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
    Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:56-63 [Conf]
  5. Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
    InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:487-494 [Conf]
  6. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
    Postplacement rewiring by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

  7. Node Mergers in the Presence of Don't Cares. [Citation Graph (, )][DBLP]

  8. Safe Delay Optimization for Physical Synthesis. [Citation Graph (, )][DBLP]

  9. Fixing Design Errors with Counterexamples and Resynthesis. [Citation Graph (, )][DBLP]

  10. Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. [Citation Graph (, )][DBLP]

  11. Customizing IP cores for system-on-chip designs using extensive external don't-cares. [Citation Graph (, )][DBLP]

  12. Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. [Citation Graph (, )][DBLP]

  13. Enhancing bug hunting using high-level symbolic simulation. [Citation Graph (, )][DBLP]

  14. Automating post-silicon debugging and repair. [Citation Graph (, )][DBLP]

  15. Reap what you sow: spare cells for post-silicon metal fix. [Citation Graph (, )][DBLP]

  16. Automating Postsilicon Debugging and Repair. [Citation Graph (, )][DBLP]

  17. Incremental Verification with Error Detection, Diagnosis, and Visualization. [Citation Graph (, )][DBLP]

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