Search the dblp DataBase

Publications of Author

1. Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
   Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. [Citation Graph (0, 0)][DBLP]
   ATVA, 2004, pp:426-440 [Conf]
   
2. Jon M. Kerridge, David Walter, Romola Guiton
   W-SQL: An Interface for Scalable, Highly Parallel Database Machines. [Citation Graph (0, 0)][DBLP]
   BNCOD, 1995, pp:263-276 [Conf]
   
3. David Walter, Jon M. Kerridge
   Large Scale Data Management and Massively Parallel Architectures in Automatic Fingerprint Recognition. [Citation Graph (0, 0)][DBLP]
   HPCN, 1994, pp:435-440 [Conf]
   
4. David Walter, Jon M. Kerridge
   The Design of the IRISS Parallel Database Machine. [Citation Graph (0, 0)][DBLP]
   HPCN Europe, 1996, pp:913-914 [Conf]
   
5. Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda
   Verification of analog/mixed-signal circuits using labeled hybrid petri nets. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:275-282 [Conf]
   
6. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
   Verification of Timed Circuits with Failure Directed Abstractions. [Citation Graph (0, 0)][DBLP]
   ICCD, 2003, pp:28-35 [Conf]
   
7. David Walter
   Systemised serendipity for producing computer art. [Citation Graph (0, 0)][DBLP]
   Computers & Graphics, 1993, v:17, n:6, pp:699-700 [Journal]
   
8. David Walter
   Computer art from Newton's, Secant, and Richardson's methods. [Citation Graph (0, 0)][DBLP]
   Computers & Graphics, 1994, v:18, n:1, pp:127-131 [Journal]
   
9. Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little
   The Case for Analog Circuit Verification. [Citation Graph (0, 0)][DBLP]
   Electr. Notes Theor. Comput. Sci., 2006, v:153, n:3, pp:53-63 [Journal]
   
10. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of timed circuits with failure-directed abstractions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:403-412 [Journal]
    
11. Scott Little, David Walter, Kevin Jones, Chris Myers
    Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:114-128 [Conf]
    
12. David Walter, Scott Little, Chris Myers
    Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. [Citation Graph (0, 0)][DBLP]
    ATVA, 2007, pp:66-81 [Conf]
    
13. 
    Symbolic Model Checking of Analog/Mixed-Signal Circuits. [Citation Graph (, )][DBLP]