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Publications of Author

1. Tiehua Du, Kah Bin Lim, Geok Soon Hong, Wei Miao Yu, Hao Zheng
   2-D Occluded Object Recognition Using Wavelets. [Citation Graph (0, 0)][DBLP]
   CIT, 2004, pp:227-232 [Conf]
   
2. Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng
   Timed circuits: a new paradigm for high-speed design. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:335-340 [Conf]
   
3. Miao Xiong, YiFan Chen, Hao Zheng, Yong Yu
   Towards Quick Understanding and Analysis of Large-Scale Ontologies. [Citation Graph (0, 0)][DBLP]
   ASWC, 2006, pp:84-98 [Conf]
   
4. Hao Zheng, Eric Mercer, Chris J. Myers
   Automatic Abstraction for Verification of Timed Circuits and Systems. [Citation Graph (0, 0)][DBLP]
   CAV, 2001, pp:182-193 [Conf]
   
5. Michael Epstein, Laszlo Hars, Raymond Krasinski, Martin Rosner, Hao Zheng
   Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts. [Citation Graph (0, 0)][DBLP]
   CHES, 2003, pp:152-165 [Conf]
   
6. Jianer Chen, Donald K. Friesen, Hao Zheng
   Tight Bound on Johnson's Algoritihm for Max-SAT. [Citation Graph (0, 0)][DBLP]
   IEEE Conference on Computational Complexity, 1997, pp:274-281 [Conf]
   
7. Di Mu, Tian Xia, Hao Zheng
   Data Dependent Jitter Characterization Based on Fourier Analysis. [Citation Graph (0, 0)][DBLP]
   DFT, 2006, pp:534-544 [Conf]
   
8. Tian Xia, Peilin Song, Hao Zheng
   Characterizing the VCO jitter due to the digital simultaneous switching noise. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:70-73 [Conf]
   
9. Hao Zheng, Kewal K. Saluja, Rajiv Jain
   Test application time reduction for scan based sequential circuits. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1995, pp:188-191 [Conf]
   
10. Brandon M. Bachman, Hao Zheng, Chris J. Myers
    Architectural Synthesis of Timed Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:354-363 [Conf]
    
11. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of Timed Circuits with Failure Directed Abstractions. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:28-35 [Conf]
    
12. Tian Xia, Hao Zheng, Jing Li, Ahmed Ginawi
    Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:218-223 [Conf]
    
13. Jianer Chen, Donald K. Friesen, Hao Zheng
    Tight Bound on Johnson's Algorithm for Maximum Satisfiability. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1999, v:58, n:3, pp:622-640 [Journal]
    
14. Hao Zheng, Eric Mercer, Chris J. Myers
    Modular verification of timed circuits using automatic abstraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1138-1153 [Journal]
    
15. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of timed circuits with failure-directed abstractions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:403-412 [Journal]
    
16. 
    Analysis on the Correlation Relationships between the Temperature Range Condition and the Genic GC Content Levels of Prokaryotes. [Citation Graph (, )][DBLP]
    
    
17. 
    A novel LDA and PCA-based hierarchical scheme for metagenomic fragment binning. [Citation Graph (, )][DBLP]
    
    
18. 
    Enriching WordNet with Folksonomies. [Citation Graph (, )][DBLP]
    
    
19. 
    Computer Simulation on the Compaction of Chromatin Fiber Induced by Salt. [Citation Graph (, )][DBLP]
    
    
20. 
    Pathway Detection Based on Hierarchical LASSO Regression Model. [Citation Graph (, )][DBLP]
    
    
21. 
    REMAS: a new regression model to identify alternative splicing events from exon array data. [Citation Graph (, )][DBLP]