The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
C. L. Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. C. L. Liu, James W. Layland
    Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. [Citation Graph (20, 0)][DBLP]
    J. ACM, 1973, v:20, n:1, pp:46-61 [Journal]
  2. W.-D. Wei, C. L. Liu
    On a Periodic Maintenance Problem. [Citation Graph (2, 0)][DBLP]
    Oper. Res. Lett., 1983, v:2, n:2, pp:90-93 [Journal]
  3. C. K. Wong, C. L. Liu, J. Apter
    A drum scheduling algorithm. [Citation Graph (0, 0)][DBLP]
    Automatentheorie und Formale Sprachen, 1973, pp:267-275 [Conf]
  4. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Low Power FPGA Design - A Re-engineering Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:656-661 [Conf]
  5. Xiangfeng Chen, Peichen Pan, C. L. Liu
    Desensitization for Power Reduction in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:795-800 [Conf]
  6. Jason Cong, Bryan Preas, C. L. Liu
    General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:709-715 [Conf]
  7. Tong Gao, Pravin M. Vaidya, C. L. Liu
    A Performance Driven Macro-Cell Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:147-152 [Conf]
  8. Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
    Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:732-737 [Conf]
  9. Taewhan Kim, C. L. Liu
    Utilization of Multiport Memories in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:298-302 [Conf]
  10. Ran Libeskind-Hadas, C. L. Liu
    Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:400-405 [Conf]
  11. Peichen Pan, Sai-keung Dong, C. L. Liu
    Optimal Graph Constraint Reduction for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:401-406 [Conf]
  12. Peichen Pan, C. L. Liu
    Partial Scan with Pre-selected Scan Signals. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:189-194 [Conf]
  13. Peichen Pan, C. L. Liu
    Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:720-725 [Conf]
  14. Prashant Saxena, C. L. Liu
    Crosstalk Minimization Using Wire Perturbations. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:100-103 [Conf]
  15. Yachyang Sun, C. L. Liu
    Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:171-176 [Conf]
  16. Junhyung Um, Taewhan Kim, C. L. Liu
    A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:98-103 [Conf]
  17. D. F. Wong, C. L. Liu
    A new algorithm for floorplan design. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:101-107 [Conf]
  18. D. F. Wong, C. L. Liu
    Array Optimization for VLSI Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:537-543 [Conf]
  19. Xianji Yao, Massaki Yamada, C. L. Liu
    A New Approach to the Pin Assignment Problem. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:566-572 [Conf]
  20. Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
    Logic Transformation for Low Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:158-162 [Conf]
  21. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
    Binary decision diagram with minimum expected path length. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:708-712 [Conf]
  22. Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
    A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:828-831 [Conf]
  23. C. L. Liu
    Sequential-machine realization using feedback shift registers [Citation Graph (0, 0)][DBLP]
    FOCS, 1964, pp:209-227 [Conf]
  24. C. L. Liu
    Pair Algebra and Its Application [Citation Graph (0, 0)][DBLP]
    FOCS, 1966, pp:103-112 [Conf]
  25. C. L. Liu
    Analysis of Sorting Algorithms [Citation Graph (0, 0)][DBLP]
    FOCS, 1971, pp:207-215 [Conf]
  26. C. L. Liu
    Optimal Scheduling on Multi-Processor Computing Systems [Citation Graph (0, 0)][DBLP]
    FOCS, 1972, pp:155-160 [Conf]
  27. Anmol Mathur, K. C. Chen, C. L. Liu
    Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:118-124 [Conf]
  28. Peichen Pan, C. L. Liu
    Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:58-64 [Conf]
  29. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:408-411 [Conf]
  30. Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
    An algorithm for synthesis of system-level interface circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:442-447 [Conf]
  31. Tong Gao, C. L. Liu
    Minimum crosstalk channel routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:692-696 [Conf]
  32. Tong Gao, C. L. Liu
    Minimum crosstalk switchbox routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:610-615 [Conf]
  33. Tong Gao, Pravo M. Vaidya, C. L. Liu
    A New Performance Driven Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:44-47 [Conf]
  34. Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. (Dave) Liu, Sung-Mo Kang
    Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:318-321 [Conf]
  35. Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
    Implication graph based domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:111-114 [Conf]
  36. Taewhan Kim, Jane W.-S. Liu, C. L. Liu
    A Scheduling Algorithm for Conditional Resource Sharing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:84-87 [Conf]
  37. Anmol Mathur, K. C. Chen, C. L. Liu
    Re-engineering of timing constrained placements for regular architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:485-490 [Conf]
  38. Anmol Mathur, C. L. Liu
    Compression-relaxation: a new approach to performance driven placement for regular architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:130-136 [Conf]
  39. Unni Narayanan, C. L. Liu
    Low power logic synthesis for XOR based circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:570-574 [Conf]
  40. Peichen Pan, C. L. Liu
    Area minimization for general floorplans. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:606-609 [Conf]
  41. Peichen Pan, Weiping Shi, C. L. Liu
    Area minimization for hierarchical floorplans. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:436-440 [Conf]
  42. Ali Pinar, C. L. Liu
    Power invariant vector sequence compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:473-476 [Conf]
  43. Prashant Saxena, C. L. Liu
    A performance-driven layer assignment algorithm for multiple interconnect trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:124-127 [Conf]
  44. Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu
    A Channel Router for Single Layer Customization Technology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:436-439 [Conf]
  45. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
    Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:486-490 [Conf]
  46. Junhyung Um, Taewhan Kim, C. L. Liu
    Optimal allocation of carry-save-adders in arithmetic optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:410-413 [Conf]
  47. Arvind K. Karandikar, Peichen Pan, C. L. Liu
    Optimal Clock Period Clustering for Sequential Circuits with Retiming. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:122-127 [Conf]
  48. Yachyang Sun, C. L. Liu
    An Area Minimizer for Floorplans with L-Shaped Regions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:383-386 [Conf]
  49. Jane W.-S. Liu, C. L. Liu
    Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1974, pp:349-353 [Conf]
  50. Chaeryung Park, Taewhan Park, C. L. Liu
    An efficient data path synthesis algorithm for behavioral-level power optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:294-297 [Conf]
  51. Ki-Seok Chung, C. L. Liu
    Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:215-220 [Conf]
  52. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware power optimization for on-chip interconnect. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:108-113 [Conf]
  53. Unni Narayanan, Peichen Pan, C. L. Liu
    Low power logic synthesis under a general delay model. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:209-214 [Conf]
  54. C. L. Liu
    Deterministic Job Scheduling in Computing Systems. [Citation Graph (0, 0)][DBLP]
    Performance, 1976, pp:241-254 [Conf]
  55. C. L. Liu
    From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1999, pp:5- [Conf]
  56. N. F. Chen, C. L. Liu
    On a Class of Scheduling Algorithms for Multiprocessors Computing Systems. [Citation Graph (0, 0)][DBLP]
    Sagamore Computer Conference, 1974, pp:1-16 [Conf]
  57. C. L. (Dave) Liu
    The High Walls have Crumpled. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:21-0 [Conf]
  58. Prashant Saxena, Peichen Pan, C. L. Liu
    The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:402-407 [Conf]
  59. Jane W.-S. Liu, C. L. Liu
    Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1978, v:10, n:, pp:95-104 [Journal]
  60. C. L. Liu, Jane W.-S. Liu, Arthur L. Liestman
    Scheduling with Slack Time. [Citation Graph (0, 0)][DBLP]
    Acta Inf., 1982, v:17, n:, pp:31-41 [Journal]
  61. Peichen Pan, Sai-keung Dong, C. L. Liu
    Optimal Graph Constraint Reduction for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1997, v:18, n:4, pp:560-574 [Journal]
  62. Peichen Pan, Weiping Shi, C. L. Liu
    Area Minimization for Hierarchical Floorplans. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1996, v:15, n:6, pp:550-571 [Journal]
  63. D. F. Wong, C. L. Liu
    Floorplan Design of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1989, v:4, n:2, pp:263-291 [Journal]
  64. C. L. Liu
    A Note on Definite Stochastic Sequential Machines [Citation Graph (0, 0)][DBLP]
    Information and Control, 1969, v:14, n:4, pp:407-421 [Journal]
  65. C. L. Liu
    Lattice Functions, Pair Algebras, and Finite-State Machines. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1969, v:16, n:3, pp:442-454 [Journal]
  66. J. L. Lewandowski, C. L. Liu, Jane W.-S. Liu
    An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 1986, v:7, n:3, pp:323-330 [Journal]
  67. Prakash V. Ramanan, Jitender S. Deogun, C. L. Liu
    A Personnel Assignment Problem. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 1984, v:5, n:1, pp:132-144 [Journal]
  68. Ki-Seok Chung, Taewhan Kim, C. L. Liu
    A Complete Model for Glitch Analysis in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:2, pp:137-154 [Journal]
  69. C. L. Liu
    Analysis and Synthesis of Sorting Algorithms. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1972, v:1, n:4, pp:290-304 [Journal]
  70. Philip K. McKinley, N. Hasan, Ran Libeskind-Hadas, C. L. Liu
    Disjoint Covers in Replicated Heterogeneous Arrays. [Citation Graph (0, 0)][DBLP]
    SIAM J. Discrete Math., 1991, v:4, n:2, pp:281-292 [Journal]
  71. C. L. Liu, K. Xie, Y. Miao, X. F. Zha, Z. J. Feng, J. Lee
    Study on the communication method for chaotic encryption in remote monitoring systems. [Citation Graph (0, 0)][DBLP]
    Soft Comput., 2006, v:10, n:3, pp:224-229 [Journal]
  72. Peichen Pan, C. L. Liu
    Partial Scan with Preselected Scan Signals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:1000-1005 [Journal]
  73. Jason Cong, C. L. Liu
    Over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:408-418 [Journal]
  74. Jason Cong, C. L. Liu
    On the k-layer planar subset and topological via minimization problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:972-981 [Journal]
  75. Jason Cong, Bryan Preas, C. L. Liu
    Physical models and efficient algorithms for over-the-cell routing in standard cell design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:723-734 [Journal]
  76. Jason Cong, Martin D. F. Wong, C. L. Liu
    A new approach to three- or four-layer channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1094-1104 [Journal]
  77. J. R. Egan, C. L. Liu
    Bipartite Folding and Partitioning of a PLA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:191-199 [Journal]
  78. Tong Gao, C. L. Liu
    Minimum crosstalk channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:465-474 [Journal]
  79. Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
    Domino logic synthesis based on implication graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:232-240 [Journal]
  80. Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu
    A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:425-438 [Journal]
  81. Anmol Mathur, C. L. Liu
    Timing-driven placement for regular architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:597-608 [Journal]
  82. Peichen Pan, Arvind K. Karandikar, C. L. Liu
    Optimal clock period clustering for sequential circuits with retiming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:489-498 [Journal]
  83. Peichen Pan, C. L. Liu
    Area minimization for floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:123-132 [Journal]
  84. Prashant Saxena, C. L. Liu
    A postprocessing algorithm for crosstalk-driven wire perturbation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:6, pp:691-702 [Journal]
  85. Prashant Saxena, C. L. Liu
    Optimization of the maximum delay of global interconnects duringlayer assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:503-515 [Journal]
  86. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
    Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:20-31 [Journal]
  87. Xianjin Yao, Masaaki Yamada, C. L. Liu
    A new approach to the pin assignment problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:999-1006 [Journal]
  88. D. T. Lee, C. L. Liu, C. K. Wong
    (g 0, g 1, ... g k)-Trees and Unary OL Systems. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1983, v:22, n:, pp:209-217 [Journal]
  89. Prakash V. Ramanan, C. L. Liu
    Permutation Representation of k-Ary Trees. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1985, v:38, n:, pp:83-98 [Journal]
  90. Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu
    Low power realization of finite state machines - a decomposition approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:3, pp:315-340 [Journal]
  91. Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
    Logic transformation for low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:265-283 [Journal]
  92. Peichen Pan, C. L. Liu
    Optimal clock period FPGA technology mapping for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:437-462 [Journal]
  93. Ali Pinar, C. L. Liu
    Compacting sequences with invariant transition frequencies. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:214-221 [Journal]
  94. Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu
    Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:5, pp:498-511 [Journal]
  95. Wei Kuan Shih, Jane W.-S. Liu, C. L. Liu
    Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1993, v:19, n:12, pp:1171-1179 [Journal]
  96. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:383-389 [Journal]
  97. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
    Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:879-887 [Journal]
  98. Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang
    Noise-aware interconnect power optimization in domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:79-89 [Journal]

  99. Generation of trees. [Citation Graph (, )][DBLP]


  100. A delay driven FPGA placement algorithm. [Citation Graph (, )][DBLP]


  101. Solution of a module orientation and rotation problem. [Citation Graph (, )][DBLP]


  102. On the k-layer planar subset and via minimization problems. [Citation Graph (, )][DBLP]


  103. Generalized latin squares I. [Citation Graph (, )][DBLP]


Search in 0.006secs, Finished in 0.663secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002