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Enrico Macii: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Daniele Masotti, Elisa Ficarra, Enrico Macii, Luca Benini
    Techniques for Enhancing Computation of DNA Curvature Molecules. [Citation Graph (0, 0)][DBLP]
    BIBE, 2004, pp:22-29 [Conf]
  2. Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini
    Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images. [Citation Graph (0, 0)][DBLP]
    CBMS, 2006, pp:413-418 [Conf]
  3. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Computational Kernels and their Application to Sequential Power Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:764-769 [Conf]
  4. Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:784-789 [Conf]
  5. Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:247-252 [Conf]
  6. Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino
    Energy-aware design techniques for differential power analysis protection. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:36-41 [Conf]
  7. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Synthesis of application-specific memories for power optimization in embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:300-303 [Conf]
  8. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:128-133 [Conf]
  9. Luca Benini, Enrico Macii, Massimo Poncino
    Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:22-27 [Conf]
  10. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
    Algorithms for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:25-30 [Conf]
  11. Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii
    Clock-tree power optimization based on RTL clock-gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:622-627 [Conf]
  12. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:467-470 [Conf]
  13. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Probabilistic Analysis of Large Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:270-275 [Conf]
  14. Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi
    In-Place Power Optimization for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:718-721 [Conf]
  15. Enrico Macii, Massoud Pedram, Fabio Somenzi
    High-Level Power Modeling, Estimation, and Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:504-511 [Conf]
  16. Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino
    Computing the Maximum Power Cycles of a Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:23-28 [Conf]
  17. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:449-450 [Conf]
  18. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    A Discrete-Time Battery Model for High-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:35-0 [Conf]
  19. Pietro Babighian, Luca Benini, Enrico Macii
    A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:500-505 [Conf]
  20. Pietro Babighian, Luca Benini, Enrico Macii
    Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:720-723 [Conf]
  21. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Enabling fine-grain leakage management by voltage anchor insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:868-873 [Conf]
  22. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Extending lifetime of portable systems by battery scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:197-203 [Conf]
  23. Luca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii
    Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:698-699 [Conf]
  24. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch Power Minimization by Gate Freezing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:163-167 [Conf]
  25. Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano
    Address Bus Encoding Techniques for System-Level Power Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:861-0 [Conf]
  26. Ashutosh Chakraborty, Prassanna Sithambaram, K. Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
    Thermal resilient bounded-skew clock tree optimization methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:832-837 [Conf]
  27. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino
    Power Estimation of Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:762-766 [Conf]
  28. Luca Macchiarulo, Luca Benini, Enrico Macii
    On-the-fly layout generation for PTL macrocells. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:546-551 [Conf]
  29. Luca Macchiarulo, Enrico Macii, Massimo Poncino
    Wire Placement for Crosstalk Energy Minimization in Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:158-162 [Conf]
  30. Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon
    A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10024-10029 [Conf]
  31. Alberto Macii, Enrico Macii, Massimo Poncino
    Improving the Efficiency of Memory Partitioning by Address Clustering. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10018-10023 [Conf]
  32. Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon
    Low-power design tools: are EDA vendors taking this matter seriously? [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1227- [Conf]
  33. Kimish Patel, Enrico Macii, Massimo Poncino
    Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:700-701 [Conf]
  34. R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    Timing Analysis of Combinational Circuits using ADD's. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:625-629 [Conf]
  35. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    A State Space Decomposition Algorithm for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:137-141 [Conf]
  36. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:214-218 [Conf]
  37. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1311-1317 [Conf]
  38. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino
    Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:8-12 [Conf]
  39. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Timed Supersetting and the Synthesis of Telescopic Units. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:331-337 [Conf]
  40. Alberto Bocca, Sabino Salerno, Enrico Macii, Massimo Poncino
    Energy-efficient bus encoding for LCD displays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:240-243 [Conf]
  41. Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro
    A novel architecture for power maskable arithmetic units. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:136-140 [Conf]
  42. Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano
    Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:77-82 [Conf]
  43. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Low-overhead state-retaining elements for low-leakage MTCMOS design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:367-370 [Conf]
  44. Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei
    Regression-based RTL power models for controllers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:147-152 [Conf]
  45. Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino
    Supporting system-level power exploration for DSP applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:17-22 [Conf]
  46. Roberto Corgnati, Enrico Macii, Massimo Poncino
    Clustered Table-Based Macromodels for RTL Power Estimation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:354-357 [Conf]
  47. Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    Enhanced clustered voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:18-23 [Conf]
  48. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:208-213 [Conf]
  49. Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello
    Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:70-0 [Conf]
  50. Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi
    Regression-Based Macromodeling for Delay Estimation of Behavioral Components. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:188-191 [Conf]
  51. Enrico Macii, Massimo Poncino
    Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:60-65 [Conf]
  52. Enrico Macii, Massimo Poncino
    Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:112-0 [Conf]
  53. Enrico Macii, Massimo Poncino
    Exact Computation of the Entropy of a Logic Circuit. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:162-167 [Conf]
  54. Enrico Macii, Massimo Poncino, Sabino Salerno
    Combining wire swapping and spacing for low-power deep-submicron buses. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:198-202 [Conf]
  55. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    STV-Cache: a leakage energy-efficient architecture for data caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:404-409 [Conf]
  56. Kimish Patel, Enrico Macii, Massimo Poncino
    Zero clustering: an approach to extend zero compression to instruction caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:56-59 [Conf]
  57. Prassanna Sithambaram, Alberto Macii, Enrico Macii
    Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:377-380 [Conf]
  58. Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
  59. R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Algebraic decision diagrams and their applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:188-191 [Conf]
  60. R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    A symbolic method to reduce power consumption of circuits containing false paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:368-371 [Conf]
  61. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Fast power estimation for deterministic input streams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:494-501 [Conf]
  62. Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino
    Parameterized RTL power models for combinational soft macros. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:284-288 [Conf]
  63. Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi
    Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:235-241 [Conf]
  64. Enrico Macii, Bernard Plessier, Fabio Somenzi
    Verification of systems containing counters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:179-182 [Conf]
  65. Kimish Patel, Enrico Macii, Luca Benini, Massimo Poncino
    Reducing cache misses by application-specific re-configurable indexing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:125-130 [Conf]
  66. Gianpiero Cabodi, Luciano Lavagno, Enrico Macii, Massimo Poncino, Stefano Quer, Paolo Camurati, Ellen Sentovich
    Enhancing FSM Traversal by Temporary Re-Encoding. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:6-11 [Conf]
  67. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:236-239 [Conf]
  68. Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino
    Energy-Efficient Color Approximation for Digital LCD Interfaces. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:81-86 [Conf]
  69. Kimish Patel, Enrico Macii, Massimo Poncino
    Frame Buffer Energy Optimization by Pixel Prediction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:98-101 [Conf]
  70. Alberto Macii, Enrico Macii, Massimo Poncino
    Increasing the locality of memory access patterns by low-overhead hardware address relocation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:385-388 [Conf]
  71. Sabino Salerno, Enrico Macii, Massimo Poncino
    Crosstalk energy reduction by temporal shielding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:749-752 [Conf]
  72. Kimish Patel, Enrico Macii, Massimo Poncino
    Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:361-364 [Conf]
  73. Luca Benini, Davide Bruni, Bruno Riccò, Alberto Macii, Enrico Macii
    An adaptive data compression scheme for memory traffic minimization in processor-based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:866-869 [Conf]
  74. Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini
    Mining Gene Sets for Measuring Similarities. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:227-232 [Conf]
  75. Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino
    Energy-efficient data scrambling on memory-processor interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:26-29 [Conf]
  76. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Discharge current steering for battery lifetime optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:118-123 [Conf]
  77. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Selective instruction compression for memory energy reduction in embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:206-211 [Conf]
  78. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    System-level power optimization of special purpose applications: the beach solution. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:24-29 [Conf]
  79. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Post-layout leakage power minimization based on distributed sleep transistor insertion. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:138-143 [Conf]
  80. R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi
    Symbolic computation of logic implications for technology-dependent low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:163-168 [Conf]
  81. Luca Macchiarulo, Enrico Macii, Massimo Poncino
    Low-energy for deep-submicron address buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:176-181 [Conf]
  82. Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:30-35 [Conf]
  83. Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino
    Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:206-211 [Conf]
  84. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:162-167 [Conf]
  85. Monica Donno, Enrico Macii, Luca Mazzoni
    Power-aware clock tree planning. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:138-147 [Conf]
  86. Roberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino
    Power Macromodeling for a High Quality RT-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:59-0 [Conf]
  87. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi
    Battery-Driven Dynamic Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:25-33 [Conf]
  88. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:250-251 [Conf]
  89. Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo
    RTL Estimation of Steering Logic Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:36-46 [Conf]
  90. B. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu
    Statistical Power Estimation of Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:197-207 [Conf]
  91. Luca Benini, Alberto Macii, Enrico Macii
    Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:314-322 [Conf]
  92. Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon
    Energy-Aware System-on-Chip for 5 GHz Wireless LANs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:166-176 [Conf]
  93. Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino
    Power Models for Semi-autonomous RTL Macros. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:14-23 [Conf]
  94. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:214-224 [Conf]
  95. Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
    Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:297-307 [Conf]
  96. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:466-476 [Conf]
  97. Sabino Salerno, Enrico Macii, Massimo Poncino
    A Low-Power Encoding Scheme for GigaByte Video Interfaces. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:58-68 [Conf]
  98. Prassanna Sithambaram, Alberto Macii, Enrico Macii
    Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:477-487 [Conf]
  99. Enrico Macii
    Leakage power optimization in standard-cell designs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:7- [Conf]
  100. Enrico Macii
    RTL power estimation and optimization. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:1- [Conf]
  101. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:74-85 [Journal]
  102. Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino
    Testing Core-Based Systems: A Symbolic Methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:4, pp:69-77 [Journal]
  103. Enrico Macii
    Guest Editor's Introduction: Dynamic Power Management of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:6-9 [Journal]
  104. R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Algebraic Decision Diagrams and Their Applications. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:171-206 [Journal]
  105. Daniele Masotti, Elisa Ficarra, Enrico Macii, Luca Benini
    Optimized Technique for Dna Structural Properties Discovering. [Citation Graph (0, 0)][DBLP]
    International Journal on Artificial Intelligence Tools, 2006, v:15, n:5, pp:695-710 [Journal]
  106. Simona Rossi, Daniele Masotti, Christine Nardini, Elena Bonora, Giovanni Romeo, Enrico Macii, Luca Benini, Stefano Volinia
    TOM: a web-based integrated approach for identification of candidate disease genes. [Citation Graph (0, 0)][DBLP]
    Nucleic Acids Research, 2006, v:34, n:Web-Server-Issue, pp:285-292 [Journal]
  107. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii, Massimo Poncino
    Discharge Current Steering for Battery Lifetime Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:985-995 [Journal]
  108. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:8, pp:769-779 [Journal]
  109. Pietro Babighian, Luca Benini, Enrico Macii
    A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:29-42 [Journal]
  110. R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1101-1115 [Journal]
  111. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Synthesis of power-managed sequential components based oncomputational kernel extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1118-1131 [Journal]
  112. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    A multilevel engine for fast power simulation of realistic inputstreams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:459-472 [Journal]
  113. Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli
    Telescopic units: a new paradigm for performance optimization of VLSI designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:220-232 [Journal]
  114. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    Automatic state space decomposition for approximate FSM traversal based on circuit analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1451-1464 [Journal]
  115. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
    Algorithms for approximate FSM traversal based on state space decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1465-1478 [Journal]
  116. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto
    Symbolic optimization of interacting controllers based onredundancy identification and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:760-772 [Journal]
  117. Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Markovian analysis of large finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1479-1493 [Journal]
  118. Enrico Macii, Bernard Plessier, Fabio Somenzi
    Formal verification of digital systems by automatic reduction of data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1136-1156 [Journal]
  119. Enrico Macii, Massoud Pedram, Fabio Somenzi
    High-level power modeling, estimation, and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1061-1079 [Journal]
  120. Elisa Ficarra, Luca Benini, Enrico Macii, G. Zuccheri
    Automated DNA fragments recognition and sizing through AFM image processing. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Technology in Biomedicine, 2005, v:9, n:4, pp:508-517 [Journal]
  121. R. Iris Bahar, Ernest T. Lampe, Enrico Macii
    Power optimization of technology-dependent circuits based on symbolic computation of logic implications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:267-293 [Journal]
  122. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:4, pp:351-375 [Journal]
  123. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Memory energy minimization by data compression: algorithms, architectures and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:255-268 [Journal]
  124. Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang H. Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis
    Early Power-Aware Design & Validation: Myth or Reality? [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:210-211 [Conf]
  125. A. Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1544-1549 [Conf]
  126. Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii
    Architectural leakage-aware management of partitioned scratchpad memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1665-1670 [Conf]
  127. K. Duraisami, Prassanna Sithambaram, A. Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
    Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1061-1064 [Conf]
  128. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  129. A. Nurrachmat, Enrico Macii, Massimo Poncino
    Low-energy pixel approximation for DVI-based LCD interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  130. Prassanna Sithambaram, Alberto Macii, Enrico Macii
    New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:232-241 [Conf]
  131. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    Power optimization of core-based systems by address bus encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:554-562 [Journal]
  132. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch power minimization by selective gate freezing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:287-298 [Journal]
  133. Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino
    Parameterized RTL power models for soft macros. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:880-887 [Journal]
  134. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Discrete-time battery models for system-level low-power design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:630-640 [Journal]
  135. Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:3, pp:417-426 [Journal]
  136. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Minimizing memory access energy in embedded systems by selective instruction compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:521-531 [Journal]
  137. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Scheduling battery usage in mobile systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1136-1143 [Journal]
  138. Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini
    Energy-Efficient Value Based Selective Refresh for Embedded DRAMS. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:70-79 [Journal]
  139. Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon
    Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:18-26 [Journal]

  140. Gene-Markers Representation for Microarray Data Integration. [Citation Graph (, )][DBLP]


  141. Segmentation of nuclei in cancer tissue images: Contrasting active contours with morphology-based approach. [Citation Graph (, )][DBLP]


  142. Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style. [Citation Graph (, )][DBLP]


  143. A Scalable Algorithmic Framework for Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  144. Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. [Citation Graph (, )][DBLP]


  145. Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. [Citation Graph (, )][DBLP]


  146. Enabling concurrent clock and power gating in an industrial design flow. [Citation Graph (, )][DBLP]


  147. Physically clustered forward body biasing for variability compensation in nanometer CMOS design. [Citation Graph (, )][DBLP]


  148. Panel: First commandment at least, do nothing well! [Citation Graph (, )][DBLP]


  149. Post-placement temperature reduction techniques. [Citation Graph (, )][DBLP]


  150. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. [Citation Graph (, )][DBLP]


  151. Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions. [Citation Graph (, )][DBLP]


  152. Temperature-insensitive synthesis using multi-vt libraries. [Citation Graph (, )][DBLP]


  153. Energy efficiency bounds of pulse-encoded buses. [Citation Graph (, )][DBLP]


  154. Optimal sleep transistor synthesis under timing and area constraints. [Citation Graph (, )][DBLP]


  155. NBTI-aware sleep transistor design for reliable power-gating. [Citation Graph (, )][DBLP]


  156. Using soft-edge flip-flops to compensate NBTI-induced delay degradation. [Citation Graph (, )][DBLP]


  157. Aging effects of leakage optimizations for caches. [Citation Graph (, )][DBLP]


  158. An integrated thermal estimation framework for industrial embedded platforms. [Citation Graph (, )][DBLP]


  159. Thermal-aware floorplanning exploration for 3D multi-core architectures. [Citation Graph (, )][DBLP]


  160. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]


  161. Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies. [Citation Graph (, )][DBLP]


  162. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. [Citation Graph (, )][DBLP]


  163. Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. [Citation Graph (, )][DBLP]


  164. Timing-driven row-based power gating. [Citation Graph (, )][DBLP]


  165. Locality-driven architectural cache sub-banking for leakage energy reduction. [Citation Graph (, )][DBLP]


  166. NBTI-aware power gating for concurrent leakage and aging optimization. [Citation Graph (, )][DBLP]


  167. Dynamic indexing: concurrent leakage and aging optimization for caches. [Citation Graph (, )][DBLP]


  168. Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. [Citation Graph (, )][DBLP]


  169. On-chip Thermal Modeling Based on SPICE Simulation. [Citation Graph (, )][DBLP]


  170. Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  171. Data-Driven Clock Gating for Digital Filters. [Citation Graph (, )][DBLP]


  172. Fully-Automated Segmentation of Tumor Areas in Tissue Confocal Images - Comparison between a Custom Unsupervised and a Supervised SVM Approach. [Citation Graph (, )][DBLP]


  173. Automated Discrimination of Pathological Regions in Tissue Images: Unsupervised Clustering vs. Supervised SVM Classification. [Citation Graph (, )][DBLP]


  174. Selection of Tumor Areas and Segmentation of Nuclear Membranes in Tissue Confocal Images: A Fully Automated Approach. [Citation Graph (, )][DBLP]


  175. MicroRNA Target Prediction and Exploration through Candidate Binding Sites Generation. [Citation Graph (, )][DBLP]


  176. An Automated Tool for Scoring Biomedical Terms Correlation Based on Semantic Analysis. [Citation Graph (, )][DBLP]


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