The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Tiantian Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author


  1. Analysis and approximation for bank selection instruction minimization on partitioned memory architecture. [Citation Graph (, )][DBLP]


  2. A Novel Process Migration Method for MPI Applications. [Citation Graph (, )][DBLP]


  3. Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking. [Citation Graph (, )][DBLP]


  4. Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks. [Citation Graph (, )][DBLP]


  5. Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002